Wireless Data Interleaving Array for Variable Spread Distance

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Solution Overview

Problem

The triangular interleaver in 5G communication systems has a constant minimum spread distance, which restricts decoding performance and fails to evenly disperse error bits during high-order modulation, leading to degradation in decoding performance and increased Block Error Ratio (BLER).

Innovation Solution

The method involves determining the size of an interleaving array with specific row and column configurations, dividing bits into subsets, and writing them into the array in a non-consecutive manner to improve the spread distance, allowing for efficient parallel write/read operations, thereby enhancing decoding performance and reducing system delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a triangular interleaver with constant minimum spread distance is used, then the interleaving structure is simple and easy to implement, but the decoding performance is restricted and error bits cannot be evenly dispersed

Engineering Contradiction:
Improveinterleaving structure simplicityVSAvoiddecoding performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies dynamics by making the minimum spread distance variable rather than constant. The improved triangular interleaver dynamically adjusts the minimum spread distance based on the row index and other parameters, allowing the spread distance to change adaptively across different positions in the interleaving array. This resolves the contradiction by maintaining structural simplicity while achieving variable spread distances that improve error dispersion and decoding performance.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of minimum spread distance from a fixed constant to a variable parameter that depends on row index and other factors. By modifying the mathematical relationship that determines spread distance, the system achieves better error bit dispersion without complicating the overall interleaving structure, thus improving decoding performance while maintaining implementation simplicity.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If consecutive encoding bits are used for high-order modulation symbols, then modulation efficiency is improved, but error bits are not evenly dispersed in a symbol period resulting in degraded decoding performance

Engineering Contradiction:
Improvemodulation efficiencyVSAvoiddecoding performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by making the interleaving characteristics position-dependent. Different rows and columns in the interleaving array have different spread distance properties, allowing local optimization of error dispersion. This enables consecutive bits to be grouped for modulation efficiency while ensuring that bits within each symbol period are sufficiently dispersed through position-specific interleaving patterns, resolving the contradiction between modulation efficiency and decoding performance.

Inventive Principle:
Principle #3Local quality

3Ease of operation

If a traditional interleaving method is used, then implementation is straightforward, but system delays increase and memory consumption is higher

Engineering Contradiction:
Improveimplementation straightforwardnessVSAvoidsystem delay
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent applies segmentation by dividing the interleaving process into structured rows and columns with specific write and read patterns. The interleaving array is segmented such that bits are written row-by-row and read column-by-column (or vice versa), creating a systematic pattern that reduces memory access complexity. This segmentation enables more efficient memory utilization and reduces system delay while maintaining straightforward implementation through regular access patterns.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses a two-dimensional interleaving array structure to transform the one-dimensional bit sequence into a two-dimensional arrangement. This dimensional change allows for more efficient memory access patterns by utilizing both row and column dimensions, reducing the time required for interleaving operations and lowering memory consumption through structured data organization while keeping the implementation straightforward.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11381342B2Method and device for interleaving data in wireless communication system
Publication Date: 2022.07.05 NOKIA TECHNOLOGIES OY
  • US11381342B2 patent drawing
  • US11381342B2 patent drawing
  • US11381342B2 patent drawing

AI summary

Embodiments of the present disclosure relate to a method and device for interleaving data in a wireless communication system. For example, a method of interleaving data in a wireless communication system comprises: determining, based on the number of a plurality of bits to be interleaved, a size of an interleaving array for interleaving the plurality of bits, wherein the number of rows is H and the number of columns is 2H-1 in the interleaving array; dividing the plurality of bits into a plurality of subsets based on the size of the interleaving array, such that an i-th subset of the plurality of subsets at most comprises 2(H-1-i)+1 consecutive bits, wherein i is a nonnegative integer smaller than H; writing the plurality of subsets respectively into the interleaving array, comprising for the i-th subset: writing an initial bit in the i-th subset into a position y(i, H-1) in an i-th row and an (H-1)-th column of the interleaving array; and writing subsequent bits of the initial bit respectively into subsequent rows of the i-th row, wherein at least two positions for writing the subsequent bits in an r-th row comprise y(r, H-1−(r-i)) and y(r, H-1+(r-i)); and reading the written plurality of bits successively column by column from the interleaving array.