Wireless Interconnect Multiprocessor Architecture for Latency Reduction
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Solution Overview
Problem
The performance of Multiprocessor Computing Apparatus (MCA) is limited by the increasing clock frequency and integration density of CMOS Integrated Circuits, which leads to heat loss, impedance issues in metallic interconnects, and global interconnection delays, making it difficult to achieve higher operating frequencies and data rates beyond 6 GHz.
Innovation Solution
The implementation of Wireless Interconnect (WLI) using Transceiver-Antenna (TRA) technology within an electromagnetically shielded Metallic Enclosure (ME) allows for direct communication between processors and shared memory units, eliminating intermediate routing and buffering delays, and enabling all-to-all direct communication links at the speed of light, while using a range of radio, microwave, and optical frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If metallic interconnects are used to connect processors and shared memory units, then data transmission is achieved, but global interconnection delays increase and operating frequency is limited to below 6 GHz
Solution Approach 1:
The patent replaces the mechanical/electrical metallic interconnect system with an electromagnetic wireless interconnect system. Transceiver-antenna (TRA) units are integrated with processors and shared memory units, enabling direct wireless communication that eliminates the physical constraints of metallic interconnects, including their RC time constants and skin effect, thereby reducing global interconnection delays and enabling higher operating frequencies
Solution Approach 2:
The patent introduces TRA units as intermediary components that facilitate direct wireless communication between processors and shared memory units. These TRA units act as mediators that eliminate the need for intermediate routing and buffering through metallic interconnect networks, allowing processors to directly access shared memory units without undergoing multiple hops through switches and routers
2Productivity
If clock frequency is increased to achieve faster computation, then processing speed improves, but heat loss in transistors and metallic interconnects increases
Solution Approach 1:
The patent substitutes the electrical current flow through metallic interconnects with electromagnetic wave transmission through wireless channels. This replacement eliminates the I²R losses and skin effect heating that occur in metallic interconnects at high frequencies, allowing faster computation without proportional increases in heat loss
Solution Approach 2:
The patent utilizes periodic electromagnetic wave transmission at various radio, microwave, and optical frequencies to transfer data between processors and shared memory units. This periodic electromagnetic action replaces continuous electrical current flow, reducing resistive heating while maintaining high data transmission rates necessary for fast processing
3Productivity
If more shared memory units are added to serve multiple processors, then memory bandwidth increases, but contention and latency for accessing shared memory increases
Solution Approach 1:
The patent segments the shared memory system into multiple independent shared memory units, each equipped with its own TRA unit. This segmentation allows processors to directly access specific memory units without contention, as each memory unit can independently communicate with multiple processors through wireless channels, thereby increasing both memory bandwidth and reducing access latency
Solution Approach 2:
The patent transitions from a hierarchical, multi-hop memory access architecture to a flat, direct wireless access architecture. By adding the wireless dimension of communication, processors can directly access any shared memory unit simultaneously without traversing through intermediate switches and routers, eliminating contention delays and reducing latency while maintaining high memory bandwidth
4Speed
If intermediate routing and buffering are used in interconnect architecture, then data transmission is achieved, but latency and contention for shared resources increases
Solution Approach 1:
The patent eliminates intermediate routing and buffering components by introducing direct wireless TRA-to-TRA communication channels between processors and shared memory units. This removes the intermediary switches, routers, and buffers that traditionally caused latency and contention, allowing data to transmit directly at the speed of light through wireless channels
Solution Approach 2:
The patent extracts and removes the intermediate routing and buffering infrastructure from the interconnect architecture. By taking out these intermediary components and replacing them with direct wireless communication paths, the system eliminates the latency and contention associated with multi-hop routing while maintaining high data transmission rates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces latency and contention for shared resources, allowing each processor to access a large number of shared memory units directly, potentially increasing operational clock frequency beyond 10 GHz and enhancing system scalability and fault tolerance.
Implementation Method 1
Wireless Interconnect (WLI) using Transceiver-Antenna (TRA) technology within an electromagnetically shielded Metallic Enclosure (ME) allows for direct communication between processors and shared memory units
Implementation Method 2
electromagnetically shielded Metallic Enclosure (ME)
Data Source
AI summary
A fan-less Multiprocessor-Computing-Apparatus (MCA) housed in a Metallic-Enclosure (ME) acting as an electromagnetic-Shield for wireless-communications/interconnects (WLI) among components of MCA enabling the whole-range-frequencies from lows of 10-HZs to highs of GHZ and beyond to be able to address almost unlimited Shared-Memory-Units (SMUs) by each processor with each SMU permanently tuned to send/receive data at a particular frequency. The ME is dust-proofed and filled with clean-air/vacuum for efficient-and-reliable WLI. The ME also acts as a heat-sink with the components of MCA placed on Circuit-Boards are mounted on inside in a plane parallel to the respective side of the ME of any required size and shape and heat producing components are firmly attached to the ME, which is waterproofed and placed-under-water for cooling. The SMUs are made up of static non-volatile Random Access Memory that can be read-from and written-to optically.