Wireless Network Central Device Synchronizing Peripheral Clocks
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Solution Overview
Problem
Existing wireless networks with peripheral devices experience asynchronies due to variations in clock behavior over time, leading to errors in data processing and difficulty in identifying and compensating for these variations.
Innovation Solution
A method and system for centrally synchronizing the execution of instructions by peripheral devices in a wireless network, which involves determining delays to align the execution of measurement instructions across devices, using a control unit, transceiver module, and synchronization unit in the central device, and a neural network to estimate and correct time differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If free-running clocks are used in peripheral devices, then device independence and simplicity are improved, but asynchronies occur between devices leading to data processing errors
Solution Approach 1:
The system uses feedback mechanisms where the central device receives data packets with timestamps from peripheral devices, calculates time differences between expected and actual reception times, and sends correction commands back to peripheral devices to adjust their clock synchronization, thereby resolving the asynchrony problem while maintaining device independence
Solution Approach 2:
The central device acts as an intermediary that coordinates time synchronization across all peripheral devices by receiving their timestamped data, computing timing offsets, and distributing synchronization corrections, enabling synchronized operation without requiring direct peer-to-peer clock coordination between peripheral devices
2Measurement precision
If clock behavior variations are compensated, then data processing accuracy is improved, but system complexity increases due to difficulty in identifying and preventing variations
Solution Approach 1:
Each peripheral device independently calculates its own time offset by comparing its transmitted timestamp with the central device's reception timestamp, and autonomously adjusts its clock accordingly, eliminating the need for complex centralized clock management while improving data processing accuracy
Solution Approach 2:
The patent replaces complex mechanical clock synchronization mechanisms with software-based timestamp comparison and digital correction algorithms, simplifying the synchronization system while achieving high precision data processing through computational rather than physical means
3Measurement precision
If transmission delays and hardware delays are accounted for, then synchronization accuracy is improved, but the difficulty of identifying and preventing asynchronies increases
Solution Approach 1:
The system performs preliminary timing measurements by exchanging test packets between central and peripheral devices before actual data acquisition, measuring transmission delays and processing times in advance, and using these pre-characterized delays to compensate for timing variations during operational data collection
Solution Approach 2:
The patent implements timeout mechanisms and deadline-based processing that skip detailed analysis of individual delay variations by enforcing strict time windows for packet reception and processing, thereby achieving synchronization accuracy through temporal constraints rather than through comprehensive delay measurement and compensation
Data Source
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AI summary
The method for centrally synchronizing the execution of instructions by peripheral devices (10) of a wireless network, which includes a central device (5), comprises executing a sequence of cycles of operations. Each cycle of operations comprises determining a reference stamp (TMD(k)) referred to a clock (23) of the central device; determining a first and a second peripheral stamp (ti,t 1(k),ti,t 2(k)) referred to a clock (31) of each peripheral device; sending to each peripheral device a respective instruction packet (Pk) including an instruction, each with a respective delay (τi(k)); determining for each peripheral device a time parameter (Ii(k)), which is a function of the first and second peripheral stamps; executing, from the time parameters, a machine -learning algorithm trained to determine, for each peripheral device, a corresponding estimation (t*MD,i(k)) of the reference stamp; and calculating the delays (τi(k+1)) relative to the cycle of operations as a function of the estimations determined by the machine-learning algorithm and the reference stamp.