Wireless Parity Backup for Flash Storage Reliability Bottlenecks
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Solution Overview
Problem
Conventional data storage devices using flash memory face reliability issues due to program failures and silent read failures, leading to data loss, and the storage of parity information in volatile SRAM increases the risk of data corruption and strains the device with additional read operations.
Innovation Solution
A data storage device controller with a wireless transceiver and security processor uses a Bluetooth interface to securely back up parity information in a cached database, utilizing a Storage Sub-System and Security Sub-System for user authentication, thereby reducing device strain and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If parity information is stored in volatile SRAM, then fast access is achieved, but data reliability deteriorates due to volatility and corruption risks
Solution Approach 1:
The system performs preliminary actions by continuously updating and maintaining parity information in SRAM while also periodically backing it up to non-volatile flash memory. This ensures that when data corruption occurs, the most recent parity is already prepared in volatile memory for immediate use, while a reliable copy exists in non-volatile memory.
Solution Approach 2:
The patent creates a copy of the parity information and stores it in both volatile SRAM and non-volatile flash memory. This copying approach allows the system to enjoy fast access from SRAM while maintaining reliability through the flash memory backup, resolving the contradiction between speed and reliability.
2Reliability
If parity information is transferred from FTL to NAND, then data protection is achieved, but device performance deteriorates due to bottlenecks
Solution Approach 1:
The patent segments the parity management function into two independent pathways: (1) FTL generates parity and stores it in SRAM for fast access, and (2) a separate background process periodically copies parity to flash memory. This segmentation eliminates the bottleneck where FTL had to directly transfer parity to NAND, as the two operations now occur independently without blocking each other.
Solution Approach 2:
The patent introduces SRAM as an intermediary buffer between FTL and NAND flash. Parity information flows from FTL to SRAM (fast volatile memory) rather than directly to NAND, and then periodically to flash backup. This intermediary approach decouples the tight coupling between FTL and NAND operations, reducing bottlenecks and improving overall device performance.
3Reliability
If FTL performs read operations from flash memory for parity, then data recovery is enabled, but device strain increases
Solution Approach 1:
The system performs preliminary action by pre-loading and maintaining parity information in SRAM during normal operation. When data recovery is needed, the system can immediately retrieve parity from SRAM without performing read operations on flash memory, thus enabling data recovery while minimizing device strain.
Solution Approach 2:
The patent implements a self-service mechanism where the system maintains its own parity information in fast SRAM memory, making it self-sufficient for data recovery operations. This eliminates the need to repeatedly read from flash memory during recovery operations, reducing device strain while maintaining full data recovery capability.
Data Source
AI summary
Embodiments described herein provide a device for storing parity information. The device includes a wireless transceiver, a memory, and an electronic processor coupled to the wireless transceiver and the memory. The electronic processor is configured to receive, with the wireless transceiver, the parity information from a data storage device controller, and store the parity information in the memory.