Wireless Rate Matching with Compact Null Bit Tracking
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Solution Overview
Problem
Existing rate matching systems in wireless communications, such as those in the 3GPP LTE standard, are inefficient due to the method of marking and removing null bits, which increases memory usage and processing time.
Innovation Solution
A method and logic circuit for rate matching that prepends null bits to bit streams, permutes, transposes, shuffles, and removes null bits based on permutation patterns, optimizing the location of null bits for efficient removal and generating a combined bit stream without the need for costly memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If null bits are marked using a full byte to represent a single bit of data, then the location of null bits can be tracked, but memory usage and processing time increase significantly
Solution Approach 1:
The patent changes the representation parameter of null bits from full byte (8 bits) to a single bit indicator. This parameter change reduces memory usage by a factor of 8 while maintaining the ability to track null bit locations through the permutation process. The system uses a compact null bit map where each bit indicates whether the corresponding position contains a null bit, rather than storing the entire byte representation.
Solution Approach 2:
The patent extracts only the essential information needed for null bit tracking (the presence/absence indicator) from the full byte representation. By taking out only the critical bit-level indicator rather than preserving the complete byte structure, the system achieves efficient memory usage while maintaining sufficient information for null bit removal after permutation operations.
2Measurement precision
If null bits are marked using a full byte to represent a single bit of data, then the location of null bits can be tracked, but processing time increases due to more memory accesses
Solution Approach 1:
The patent changes the data structure parameter from byte-level representation to bit-level representation for null bit tracking. This parameter change reduces the number of memory accesses required during permutation operations, as the compact bit map requires fewer reads and writes compared to full byte representations, thereby reducing processing time while maintaining accurate null bit location tracking.
Solution Approach 2:
The patent segments the null bit information into individual bit positions within a compact map structure. This segmentation allows the system to access and manipulate null bit indicators efficiently at the bit level rather than requiring byte-level operations, reducing the overall number of memory accesses and improving processing speed during the permutation and null bit removal processes.
3Manufacturing precision
If null bits are removed after all bit ordering operations, then the correct combined bit stream is generated, but the system requires more memory accesses and longer processing time
Solution Approach 1:
The patent performs preliminary marking of null bit positions before the permutation and bit ordering operations using a compact bit map. This preliminary action allows the system to track null bit locations through all transformations without requiring expensive full-byte representations. The null bit information is prepared in advance in an efficient format that enables quick identification and removal after the bit stream operations are complete.
Solution Approach 2:
The patent changes the internal representation parameter of null bit information from full byte to single bit throughout the processing pipeline. This parameter change maintains manufacturing precision for generating the correct combined bit stream while significantly improving productivity by reducing memory access overhead and processing time during the rate matching operations.
Data Source
AI summary
A method and a logic circuit for rate matching for three equally sized bit streams, including: prepending each of the bit streams with null bits; permuting the first two bit streams according to a first permutation pattern; permuting the third bit stream based on the first permutation pattern; transposing the three bit streams; shuffling the second and third bit streams; removing the null bits from the first bit stream and from the shuffled bit stream, wherein location of the null bits in the first bit stream is based only on a number of prepended null bits and the first permutation pattern and location of the null bits in the shuffled bit stream is based only on the number of prepended null bits, the first permutation pattern, and a null index related to the number of prepended null bits; and generating a combined bit stream from the three bit streams.