Wireless Telemetry Processor Segmentation and Clock Synchronization

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Solution Overview

Problem

Existing wireless communication systems between electronic devices, such as medical devices and remote devices, often intertwine control of telemetry operations with device functions, leading to complexities in managing and synchronizing data exchanges effectively.

Innovation Solution

The system separates processing into two independent processors, one for wireless communications and another for device functions, with a separate clock circuit generating timing signals to synchronize data exchanges, ensuring that wireless communications and device operations are controlled independently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If control of telemetry operations is separated from device function operations into two independent processors, then reliability and independence of operations are improved, but device complexity increases

Engineering Contradiction:
Improvereliability of telemetry and device function operationsVSAvoidcomplexity of processor architecture
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system is divided into two independent processors: a first processor dedicated to telemetry operations (wireless communications) and a second processor dedicated to device function operations. This segmentation allows each processor to operate independently without interference, improving reliability while managing complexity through functional separation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A separate clock circuit acts as an intermediary between the two processors, providing synchronized timing signals to both. This mediator ensures coordinated operation between the independent processors without requiring direct complex interaction between them, simplifying the overall system architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If a separate clock circuit is introduced to synchronize data exchanges between processors, then synchronization precision is improved, but device complexity increases

Engineering Contradiction:
Improvesynchronization precision of data exchangeVSAvoidcomplexity of timing synchronization system
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

A dedicated clock circuit serves as an intermediary timing source that provides synchronized clock signals to both processors. This separate timing source ensures precise synchronization of data exchanges between the independent processors without requiring complex synchronization protocols or inter-processor communication mechanisms.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The separate clock circuit provides universal timing signals that serve both the first processor (telemetry operations) and the second processor (device function operations). This multi-functional timing source simplifies the system by providing a single synchronization mechanism for multiple independent components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8117481B2Apparatus and method for processing wirelessly communicated information within an electronic device
Publication Date: 2012.02.14 ROCHE DIABETES CARE INC
  • US8117481B2 patent drawing
  • US8117481B2 patent drawing
  • US8117481B2 patent drawing

AI summary

An electronic device (12) for processing information wirelessly received from another electronic device (14) or to be wirelessly sent to the another electronic device (14) may include a first processor (20) that controls only wireless communications with the another electronic device (14) and excluding operations associated only with the electronic device (12), a second processor (16) that controls the operations associated only with the electronic device (12) and excluding the wireless communications with the another device (14), and a clock circuit (24, 190) that is separate and independent from the first and second processors (20, 16) and that produces at least one timing signal that regulates synchronous exchange of the information between the first and second processors (20, 16).