Wireless Timing Synchronization Using Delta-Sigma Modulation

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Solution Overview

Problem

In wireless networks, achieving precise timing synchronization while minimizing power consumption and cost is challenging due to the high power usage and expense of precise clocks, and wider timeslots inefficiently use communication bandwidth and increase receiver power consumption.

Innovation Solution

A system for synchronizing nodes in a wireless network using a delta-sigma timing modulator that adjusts the clock of a second node to minimize timing errors, allowing for reduced guardbands and keep-alive intervals, and utilizing a parent-tracking system to maintain synchronization without the need for expensive crystal calibration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If precise clocks are used at each transmitter and receiver to maintain aligned timeslots, then timing synchronization accuracy is improved, but power consumption and manufacturing cost increase

Engineering Contradiction:
Improvetiming synchronization accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent replaces expensive, high-precision clocks with inexpensive, lower-precision clocks at each node. Instead of relying on each node's clock being inherently accurate, the system uses a master clock that periodically synchronizes all nodes, allowing cheap clocks to be used while maintaining overall network synchronization accuracy.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent introduces a master clock as an intermediary time reference that all nodes synchronize to. This master clock acts as a central coordinator, providing timing information to slave nodes so that they can maintain synchronized timeslots without needing inherently precise local clocks, thus reducing power consumption and cost.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If wider timeslots are used to accommodate clock drift, then timing synchronization robustness is improved, but communication bandwidth efficiency and receiver power consumption worsen

Engineering Contradiction:
Improvesynchronization robustnessVSAvoidbandwidth efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements a feedback mechanism where the master clock monitors timing deviations from slave nodes and sends correction signals to adjust their timeslots. This allows the system to maintain tight synchronization with narrow timeslots while compensating for clock drift through continuous feedback, thereby preserving bandwidth efficiency while ensuring synchronization robustness.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent makes the timeslot structure dynamic by allowing the master clock to adjust slave node timing based on observed drift. Instead of using fixed, wide timeslots to accommodate maximum expected drift, the system dynamically adjusts timing parameters based on actual performance, enabling narrow timeslots while maintaining robustness against drift through active management.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9955443B2Timing synchronization for wireless networks
Publication Date: 2018.04.24 ANALOG DEVICES INT UNLTD CO
  • US9955443B2 patent drawing
  • US9955443B2 patent drawing
  • US9955443B2 patent drawing

AI summary

A system for synchronizing nodes in a wireless network comprises a first node and a second node. The first node comprising a transmitter, a receiver, and a first time keeper. The second node comprising a transmitter, a receiver, a second time keeper, a timing error measurer for making a timing error measurement between the first time keeper and the second time keeper. The second timekeeper is adjusted to target minimizing the timing error measurement.