Wireless Video Pixel Clock Recovery With Low-Jitter Synchronization
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Solution Overview
Problem
Current wireless video transmission systems face challenges in synchronizing video signals over long distances without the use of cables, particularly in aesthetic and installation-convenient setups, such as hanging flat-screen displays or projectors, where high-bandwidth and high-performance wireless communication is required.
Innovation Solution
A wireless video communication system that includes a wireless video receiver with a clock generator capable of generating a pixel clock signal synchronized to a synchronization signal, utilizing a first clock generation module to produce an intermediate clock signal and a second module to generate the pixel clock signal, ensuring a clock rate at least ten times higher than the intermediate clock rate, and capable of producing low latency and minimal clock jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If wireless video transmission is used to eliminate cables for aesthetic and installation convenience, then ease of operation is improved, but reliability of signal synchronization deteriorates
Solution Approach 1:
The patent introduces a synchronization signal as an intermediary component transmitted alongside video data. This synchronization signal serves as a reference that enables the receiver to accurately reconstruct the pixel clock signal, thereby maintaining reliable signal synchronization even over wireless transmission distances without requiring physical cable connections.
2Manufacturing precision
If high pixel clock rates are used for high-definition video transmission, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the clock generation process into two distinct modules: a digital phase-locked loop for generating an intermediate clock signal, and an analog phase-locked loop for generating the final high-rate pixel clock signal. This segmentation allows each module to operate at optimized clock rates, achieving high pixel clock accuracy without requiring the entire system to operate at the high clock rate simultaneously, thereby reducing overall device complexity.
3Ease of manufacture
If digital PLL is used for clock generation, then ease of manufacture is improved, but manufacturing precision of high-rate clock signal deteriorates
Solution Approach 1:
The patent merges digital and analog phase-locked loop technologies in a hybrid clock generation system. The digital PLL generates an intermediate clock signal with good stability and ease of manufacture, while the analog PLL uses this intermediate signal to generate the final high-rate pixel clock signal with superior accuracy. This combination leverages the advantages of both digital and analog approaches, achieving high manufacturing precision for the pixel clock signal while maintaining ease of manufacture through modular design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient wireless transmission of high-definition video signals with synchronized pixel clock signals, achieving low latency and minimal clock jitter, thus ensuring high-quality video display without the need for physical cables.
Implementation Method 1
The first clock generation module may include a digital phase-locked loop
Implementation Method 2
the second clock generation module may include an analog phase-locked loop
Data Source
AI summary
Some demonstrative embodiments include devices, systems and/or methods of wireless video communication. Some embodiments include a wireless video receiver to receive a wireless video transmission including data representing pixels of a video frame and a synchronization signal indicative of a beginning of the video frame, the wireless receiver including a clock generator to generate a pixel clock signal synchronized to the synchronization signal, wherein a clock rate of the pixel clock signal corresponds to a pixel rate of the pixels. Other embodiments are described and claimed.