Wireline Transceiver Clock Switching for Accuracy and Power Balance
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Solution Overview
Problem
High-speed wireline transceivers face challenges with accurate and stable clock signals, as external clock sources are expensive and increase device size and power consumption, while onboard clock generation also poses cost, size, and power consumption issues.
Innovation Solution
An integrated circuit device with dual clock paths for external and internal clock signal generation, including biasing circuitry and selector circuitry to choose between external and internal clock outputs based on user input, and onboard clock generation using a frequency reference signal from a passive resonator, with calibration circuitry to set the capacitance of variable loading capacitors for precise clock signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external clock sources are used, then accurate and stable clock signals are achieved, but device cost, size, and power consumption increase
Solution Approach 1:
The clock path is divided into two separate segments: an external clock path for high-accuracy applications and an internal clock generation path for cost-sensitive applications. This segmentation allows the system to choose the appropriate path based on requirements, reducing the need for always including expensive external clock components.
Solution Approach 2:
A clock selector circuit acts as an intermediary between the external clock source and the internal functional circuitry. This selector can route either the external clock signal or the internally generated clock signal to the functional blocks, enabling flexible clock source selection and reducing overall system complexity.
2Reliability
If external clock sources are used, then accurate clock signals are achieved, but power consumption increases
Solution Approach 1:
The clock source configuration is made dynamic through the clock selector circuit, which can switch between external and internal clock sources based on power management requirements. This dynamic selection allows the system to optimize power consumption by using lower-power internal clock generation when high accuracy is not critical.
3Device complexity
If onboard clock generation is implemented, then device cost is reduced, but clock signal accuracy and stability deteriorate
Solution Approach 1:
The integrated circuit is designed with universal clock input capability that can accept both external clock signals and external frequency reference signals. This multi-functionality allows the same device to serve both cost-sensitive applications (using internal generation) and accuracy-critical applications (using external sources), maintaining versatility while reducing cost for appropriate applications.
4Adaptability or versatility
If dual clock paths with selector circuitry are implemented, then flexibility and user choice are improved, but device complexity increases
Solution Approach 1:
The external clock path and internal clock generation path are merged into a unified clock distribution architecture. Both paths converge at the clock selector, which then distributes the selected clock signal to all functional circuitry. This merging approach provides flexibility while avoiding the need for completely separate clock distribution networks.
Data Source
AI summary
An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.