Wireline Receiver Timing Recovery with Threshold-Triggered DFE Adaptation
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Solution Overview
Problem
Conventional Ethernet PHY receivers experience long link-up times and dead-lock conditions due to the interdependence of timing error detection loops and adaptive decision feedback equalizers, especially in short channels with low inter-symbol interference and certain modulation types, leading to inefficient convergence.
Innovation Solution
A method involving initial sampling at a frequency higher than the symbol frequency, followed by digital equalization and adaptive tap weight adjustment, with error measurement triggering phase adjustment of the sampling clock to facilitate rapid convergence of equalization and timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing error detection loop and adaptive decision feedback equalizer are used simultaneously in conventional Ethernet PHY receivers, then channel distortion compensation and timing recovery are achieved, but link-up time is extended and dead-lock conditions occur due to their interdependence
Solution Approach 1:
The patent applies preliminary action by initializing the sampling clock at a frequency higher than the symbol frequency before equalizer adaptation begins. This preliminary frequency setting allows the equalizer to converge more rapidly on its tap weights without the timing loop actively adjusting phase during the critical convergence phase, thereby preventing dead-lock conditions and reducing overall link-up time.
Solution Approach 2:
The patent segments the timing recovery and equalization processes into distinct phases: an initialization phase where the sampling clock runs at a fixed higher frequency to allow equalizer convergence, followed by a synchronization phase where the timing loop engages for fine-tuning. This segmentation eliminates the harmful interdependence that causes dead-lock while maintaining both functions' benefits.
2Productivity
If sampling clock frequency is increased above symbol frequency for rapid equalizer convergence, then equalization speed is improved, but timing accuracy deteriorates until phase adjustment is applied
Solution Approach 1:
The sampling clock is preliminarily set to a higher frequency to accelerate equalizer convergence during the initialization phase. Once the equalizer has converged (indicated by error measurement crossing a threshold), the timing loop then applies phase adjustment to correct the sampling timing accuracy, thereby achieving both rapid convergence and accurate timing.
Solution Approach 2:
The system employs periodic phase adjustment through the timing loop after the initial high-frequency sampling phase. The timing error detection loop periodically corrects the sampling clock phase based on measured errors, ensuring that timing accuracy is maintained while benefiting from the faster initial convergence achieved through high-frequency sampling.
Data Source
AI summary
A network communications receiver and a method of operating the same in symbol timing recovery and equalization adaptation. A data converter samples a received analog signal at an initialization frequency higher than the symbol frequency of the received signal, and converts the samples to a digital sample stream. A decision feedback equalizer including a digital filter with one or more tap weights is adapted, and an error measurement obtained from the output of the decision feedback equalizer. In response to the error measurement crossing an error threshold value, a timing loop including timing error detection is initiated to adjust the phase of the sampling clock applied to the data converter.