Semiconductor Wiring Air Gap Formation via Sacrificial Layer Removal
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Solution Overview
Problem
As semiconductor devices integrate to higher densities, parasitic capacitance between neighboring wiring patterns increases, reducing operational speed, and existing methods fail to effectively form air gaps to mitigate this issue.
Innovation Solution
A method involving the formation of a sacrificial layer on a substrate, followed by plasma treatment and wet etching to create air gaps between wiring patterns, using silicon oxide with hydrocarbon groups and specific plasma conditions to enhance hydrophilicity and etching selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wiring patterns are placed closer together to increase integration density, then device integration density is improved, but parasitic capacitance between neighboring wiring patterns increases
Solution Approach 1:
The patent extracts the harmful dielectric material between wiring patterns and replaces it with air gaps. By removing the solid dielectric material that causes parasitic capacitance and replacing it with air (vacuum), the harmful capacitive coupling between adjacent wiring patterns is eliminated while maintaining the high integration density layout
Solution Approach 2:
The patent introduces porous air gaps between wiring patterns instead of solid dielectric material. These air gaps act as porous structures with air-filled voids, providing low dielectric constant regions that reduce parasitic capacitance while allowing the wiring patterns to remain closely spaced for high integration density
2Speed
If air gaps are formed between wiring patterns to reduce parasitic capacitance, then operational speed is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary action by forming sacrificial layers in strategic positions before wiring pattern formation. These sacrificial layers are deposited and patterned in advance, creating templates that guide subsequent self-aligned etching processes to form air gaps, thereby simplifying the overall manufacturing process despite the added initial steps
Solution Approach 2:
The patent uses sacrificial layers as intermediary materials to facilitate air gap formation. These temporary sacrificial layers serve as mediators that enable precise air gap creation through self-aligned etching, and are later removed to leave the desired air gap structures, simplifying the manufacturing process by providing a controlled intermediate step
3Manufacturing precision
If sacrificial layer is treated with plasma to enhance hydrophilicity for better wet etching removal, then etching selectivity is improved, but process parameters and time are increased
Solution Approach 1:
The patent applies parameter changes by modifying the physical and chemical properties of the sacrificial layer through plasma treatment. The plasma exposure alters the surface chemistry and hydrophilicity of the sacrificial layer, enhancing its responsiveness to wet etchants and improving etching selectivity, which allows for more precise and faster air gap formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance by forming uniform air gaps, improving the operational speed and reliability of semiconductor devices.
Implementation Method 1
The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment
Implementation Method 2
The modified sacrificial layer is removed by a wet etching process
Data Source
AI summary
Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.