Wiring Structure Barrier Layer Prevents Crown-Like Defects
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Solution Overview
Problem
The narrowing line width of copper wires in photo-lithography and etching processes leads to misalignment and over-etching issues, resulting in crown-like defects due to Galvanic reactions between copper and gold layers with different oxidation potentials, causing copper erosion and coloration of the gold-plated layer.
Innovation Solution
A wiring structure comprising a substrate, a seed layer, a copper layer, a barrier layer with an oxidation potential greater than copper, and an anti-oxidation layer that covers exposed surfaces, preventing Galvanic reactions by forming the barrier layer as an anode and copper as a cathode during etching, and applying the anti-oxidation layer post-etching to prevent copper erosion and coloration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If copper wire line width is narrowed to improve integration density, then productivity and chip throughput improve, but manufacturing precision deteriorates due to misalignment and over-etching
Solution Approach 1:
A barrier layer is formed on the copper layer before the etching process to prevent excessive etching and protect the copper wire structure during fabrication, thereby maintaining manufacturing precision while enabling narrower line widths for higher productivity
2Manufacturing precision
If copper layer is etched to form wiring layer, then manufacturing precision improves by defining wire patterns, but crown-like defects occur due to Galvanic reaction between copper and gold layers
Solution Approach 1:
A barrier layer is introduced as an intermediary between the copper layer and the etchant, preventing direct contact and Galvanic reaction while allowing the etching process to define the wiring patterns with precision without causing crown-like defects
Solution Approach 2:
The harmful Galvanic reaction is eliminated by removing the direct electrochemical pathway between copper and gold layers through the insertion of a barrier layer, extracting the harmful interaction from the system
3Reliability
If barrier layer is added to prevent Galvanic reaction, then reliability improves by preventing copper erosion, but device complexity increases due to additional layers
Solution Approach 1:
The barrier layer serves multiple functions simultaneously: it prevents Galvanic reaction between copper and gold, protects the copper layer from erosion during etching, and provides a foundation for the anti-oxidation layer, thereby improving reliability without proportionally increasing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses crown-like defects by preventing copper erosion and coloration of the gold-plated layer, enhancing the anti-oxidation properties and improving the throughput of chip fabrication by avoiding Galvanic reactions and maintaining the integrity of the copper layer.
Implementation Method 1
the copper wire has the Galvanic reaction when the exposed copper wire and the gold-plated layer on the wiring surface concurrently contact with the etchant because the copper and the gold have different oxidation potentials
Implementation Method 2
the metal materials with different oxidation potentials concurrently in the etchant produce the electrochemical reaction due to the potential difference
Implementation Method 3
an anti-oxidation layer comprehensively covers exposed surfaces of the barrier layer and the wiring layer
Implementation Method 4
the copper layer and a portion of the seed layer are etched to form a wiring layer
Data Source
AI summary
A wiring structure for improving a crown-like defect and a fabrication method thereof are provided. The method includes the following steps. A substrate, on which a seed layer and a patterned photoresist layer with an opening are formed, is provided. A copper layer, having a bottom covering the seed layer, is formed in the opening. A barrier layer covering at least one top portion of the copper layer is formed on the copper layer. An oxidation potential of the barrier layer is greater than that of the copper layer. The patterned photoresist layer is removed to perform an etching process, wherein the copper layer and a portion of the seed layer exposed are etched to form a wiring layer. An immersion process is performed to form an anti-oxidation layer comprehensively on exposed surfaces of the barrier layer and the wiring layer.