Layered Wiring Board Openings for Multi-Size Chip Mounting
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Solution Overview
Problem
The challenge in semiconductor packaging is the need for miniaturization and versatility in wiring boards to accommodate semiconductor chips of varying sizes, as existing designs require redesigning the board when chip components change in size, leading to increased complexity and space usage.
Innovation Solution
A wiring board design featuring multiple layers with differently sized pad regions, allowing for the mounting of chip components of various sizes without requiring a new board, achieved by strategically arranging connection pads in different layers to reduce the size of mounting regions and minimize the area occupied by chip components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the wiring board is redesigned when chip component size changes, then the board can accommodate different chip sizes, but the complexity of the design process increases and production time is lost
Solution Approach 1:
The wiring board is designed with multiple pad regions of different sizes (first pad region, second pad region, third pad region) that can accommodate various chip component sizes. The board includes a first mounting region for larger chips and a second mounting region for smaller chips, allowing a single board design to serve multiple chip size requirements without redesign
Solution Approach 2:
The patent utilizes vertical layering with multiple insulating layers and conductive layers to create three-dimensional pad regions at different heights. This vertical arrangement allows different sized pads to coexist on the same board plane, enabling versatility without increasing horizontal footprint or requiring multiple board designs
2Adaptability or versatility
If larger pad regions are provided for all chips, then all chip sizes can be mounted, but the board area occupied increases and solder resist amount increases
Solution Approach 1:
Different pad regions are provided with different sizes and shapes according to the specific mounting requirements. The first pad region has a first size for larger chips, while the second and third pad regions have smaller sizes for smaller chips. This localized differentiation allows each pad to be optimally sized for its intended chip, minimizing total board area usage
Solution Approach 2:
The board is segmented into multiple distinct pad regions (first, second, and third pad regions) with different dimensions. Each segment is optimized for specific chip sizes, allowing efficient space utilization rather than providing uniform large pads across the entire board
3Area of stationary object
If pad regions are made smaller to reduce board area, then board size is reduced, but the distance between pads becomes narrow making conductive layer formation difficult
Solution Approach 1:
The patent creates conductive paths in the vertical dimension by forming conductive layers between insulating layers. This vertical routing allows electrical connection between closely spaced pad regions without requiring long horizontal traces, maintaining manufacturability even when horizontal pad distances are reduced
Solution Approach 2:
The conductive layers are formed between insulating layers during the board manufacturing process, establishing electrical connections before final assembly. This preliminary formation of conductive paths ensures that even narrow pad distances can be reliably connected through pre-established vias and conductive vias
Data Source
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AI summary
A wiring board includes: a first insulating layer; a first pad region provided above the first insulating layer and having a first connection pad; a second insulating layer provided above the first connection pad and having a first opening to expose the first connection pad; a second pad region provided above the second insulating layer and having a second connection pad electrically connected to the first connection pad; and a third insulating layer provided above the second connection pad , and having a second opening to exposes the first and second connection pads. The first connection pad region is smaller than the second connection pad region.