Wiring Board Inductor Shielding and Warping Control
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Solution Overview
Problem
Existing wiring boards with laminated inductors face challenges in achieving desired inductor characteristics such as inductance and Q factor due to magnetic flux inhibition by planar conductors, leading to issues with power supply stability and efficiency, especially in low-voltage microprocessor applications.
Innovation Solution
A wiring board design featuring a laminated-inductor forming section with strategically positioned inductor patterns and via conductors, where the uppermost inductor pattern is separated by 100 μm or more from the upper planar conductor, and the lowermost inductor pattern is similarly separated from the lower planar conductor, using multiple insulation layers and reinforcing materials to enhance rigidity and reduce warping, while maintaining electromagnetic shielding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the uppermost inductor pattern is positioned close to the planar conductor for compact design, then the device complexity is reduced, but the inductor characteristics (inductance and Q factor) deteriorate due to magnetic flux inhibition
Solution Approach 1:
The patent positions the uppermost inductor pattern at a specific distance (100 μm or more) from the planar conductor in the vertical dimension (thickness direction), resolving the contradiction by utilizing spatial separation in the Z-direction rather than increasing planar area. This dimensional approach maintains compactness while ensuring adequate magnetic flux path.
2Stability of the object's composition
If multiple insulation layers and reinforcing materials are added to reduce warping and enhance rigidity, then the stability of the substrate is improved, but the device complexity increases
Solution Approach 1:
The patent employs a composite layer structure combining multiple insulation layers (first insulation layer, second insulation layer) with reinforcing materials strategically positioned to counteract warping forces. This composite approach enhances substrate stability while managing the complexity through functional integration of each layer.
Solution Approach 2:
Reinforcing materials are selectively positioned in specific regions of the substrate where warping stress is most critical, rather than uniformly distributing complexity throughout the entire structure. This local quality approach optimizes warping resistance while minimizing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves desired inductor characteristics by minimizing magnetic flux inhibition, ensuring stable power supply and efficient inductance, and reducing warping and thermal contraction, thus enhancing the performance of low-voltage microprocessors in mobile devices.
Implementation Method 1
a planar conductor formed on the second insulation layer of the substrate and formed to shield electromagnetic force generated from the laminated-inductor forming portion of the substrate
Implementation Method 2
the uppermost inductor pattern has a distance of 100 μm or more from the planar conductor
Data Source
AI summary
A wiring board includes a substrate having a laminated-inductor forming portion and including multiple first insulation layers and a second insulation layer formed on a first side of the first insulation layers such that the first insulation layers have the laminated-inductor forming portion, and a planar conductor formed on the second insulation layer of the substrate and formed to shield electromagnetic force generated from the laminated-inductor forming portion of the substrate. The laminated-inductor forming portion of the substrate has multiple inductor patterns formed on the first insulation layers and multiple via conductors connecting the inductor patterns through the first insulation layers, and the inductor patterns include an uppermost inductor pattern formed between the second insulation layer and the first insulation layers such that the uppermost inductor pattern has a distance of 100 μm or more from the planar conductor.