Wiring Board Inductor Via Alignment to Reduce Eddy Currents
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Solution Overview
Problem
Existing wiring boards face challenges in achieving desired inductor characteristics such as inductance and Q factor due to interference from plain conductors and eddy currents, particularly when insulation layers are thin and conductive patterns are fine-pitched, leading to compromised magnetic flux and inductor performance.
Innovation Solution
A wiring board design featuring multiple insulation layers with inductor patterns and via conductors, a land structure, and a plain conductor with a third via conductor connecting the plain conductor and land structure, where the central axis of the third via conductor passes through the projected region of the second via conductor, ensuring separation and reduced interference from plain conductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If plain conductors are formed on insulation layers to connect inductor patterns, then electrical connectivity is improved, but magnetic flux interference and eddy current impact increase, degrading inductor characteristics
Solution Approach 1:
The harmful plain conductor is extracted and removed from the insulation layer adjacent to the inductor. Instead, a via conductor structure is used that connects through the insulation layer without forming a continuous plain conductor surface, thereby eliminating the source of eddy currents and magnetic flux interference while maintaining necessary electrical connectivity.
Solution Approach 2:
A via conductor serves as an intermediary element that provides electrical connection between different inductor patterns through the insulation layer without creating a harmful plain conductor. The via conductor is a localized conductive path that avoids the continuous conductive surface that causes eddy currents, thus mediating between the need for connectivity and the need to minimize electromagnetic interference.
2Productivity
If insulation layer thickness is reduced to achieve finer pitch conductive patterns, then device integration is improved, but inductor characteristics deteriorate due to increased interference from plain conductors
Solution Approach 1:
The harmful plain conductor is extracted from the structure, allowing insulation layers to be made thinner without compromising inductor performance. By removing the continuous conductive surface that causes interference, the design enables finer pitch patterns and better integration while maintaining desired inductor characteristics.
Solution Approach 2:
The conductive structure is changed from a continuous plain conductor to a localized via conductor configuration. This local quality change allows the insulation layer thickness to be reduced for better integration, as the localized via structure does not create the same level of electromagnetic interference as a continuous plain conductor would in a thinner layer.
3Reliability
If via conductors are positioned to align with land structures for electrical connection, then connectivity is improved, but magnetic flux interference increases when the alignment causes plain conductors to overlap with inductor patterns
Solution Approach 1:
The harmful overlapping plain conductor structure is extracted and removed. Instead of allowing via conductors to align directly with land structures in a way that creates continuous conductive paths over the inductor, the design uses a via conductor configuration that connects through the insulation layer without creating harmful conductive loops or continuous paths that would generate eddy currents.
Solution Approach 2:
The via conductor acts as an intermediary that provides necessary electrical connection while avoiding direct alignment with land structures that would create harmful conductive paths. The via conductor is positioned to connect through the insulation layer without forming continuous conductive surfaces over the inductor patterns, thus mediating between connectivity requirements and electromagnetic interference prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively achieves desired inductor characteristics by minimizing magnetic flux interference and eddy current impact, enhancing inductance and Q factor performance while maintaining structural integrity and reducing warping.
Implementation Method 1
first via conductors formed in the first insulation layers, respectively, such that the first via conductors are connecting the inductor patterns through the first insulation layers
Implementation Method 2
second via conductor formed in the second insulation layer such that the second via conductor is connecting the land structure and the outermost inductor pattern
Implementation Method 3
third via conductor formed in the third insulation layer such that the third via conductor is connecting the plain conductor and the land structure and has the central axis passing through the center of the third via conductor inside a projected region of the second via conductor
Data Source
AI summary
A wiring board includes a substrate including first insulation layers, a second insulation layer on the first layers, a third insulation layer on the second layer, and a plain conductor on the third layer. The substrate has inductor forming portion in which inductor patterns are formed on the first layers and first via conductors formed in the first layers such that the first via conductors connect the inductor patterns through the first layers, the substrate has a land on the second layer and a second via conductor in the second layer such that the second via conductor connects the land and the outermost inductor pattern, the substrate has a third via conductor in the third layer such that the third via conductor connects the plain conductor and land and has the central axis passing through the center of the third via conductor inside projected region of the second via conductor.


