Wiring Board Recessed Interconnect Layer Solder Bridge Prevention
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Solution Overview
Problem
In existing semiconductor devices with flip-chip mounted semiconductor chips on wiring boards, the exposed interconnect layer pads can cause solder to flow onto the insulating layer, leading to solder bridges and short-circuiting, especially as the distance between pads narrows, reducing insulation reliability.
Innovation Solution
A wiring board design featuring a single-layer insulating layer with a single-layer interconnect layer where the entire upper surface of the interconnect layer is recessed relative to the insulating layer, and the lower surface is partially exposed, preventing solder from flowing onto the insulating layer during chip mounting by creating a step that acts as a dam.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the interconnect layer surface is exposed at the same plane as the insulating layer surface, then the mounting process is simplified, but solder flows onto the insulating layer causing short-circuiting between adjacent pads
Solution Approach 1:
The patent transitions from a two-dimensional planar exposure to a three-dimensional recessed structure. The interconnect layer is exposed at a lower level than the insulating layer surface, creating a vertical dimension that prevents solder from flowing onto the insulating layer while maintaining pad accessibility for mounting operations.
Solution Approach 2:
The patent introduces an underfill resin as an intermediary substance that fills the recessed area between the interconnect layer and the insulating layer. This underfill resin acts as a barrier to prevent solder from reaching the insulating layer surface, while still allowing electrical connection between the semiconductor chip electrodes and the interconnect layer pads.
2Area of stationary object
If the interval between adjacent pads is narrowed to increase density, then the wiring board area is reduced, but solder bridges form more easily causing short-circuiting
Solution Approach 1:
By creating a recessed structure with vertical depth, the patent adds a third dimension to the pad structure. This allows pads to be positioned closer together horizontally while the vertical recess with underfill resin provides sufficient solder containment, effectively decoupling the horizontal pad spacing from the vertical solder flow path.
Solution Approach 2:
The underfill resin serves as a protective intermediary that fills the recessed space between closely spaced pads. This intermediary material prevents solder from bridging between adjacent pads even when the horizontal interval is minimized, enabling higher pad density while maintaining insulation reliability.
3Reliability
If a metal film is formed on the pad surface to improve solder wettability, then solder bonding is enhanced, but the risk of solder bridge formation increases
Solution Approach 1:
The underfill resin acts as a spatial intermediary that physically separates the solder from the insulating layer surface. This allows the metal film to remain on the pad surface for optimal solder wettability and bonding, while the underfill resin prevents excess solder from reaching the insulating layer and forming bridges between adjacent pads.
Solution Approach 2:
The patent applies different properties to different regions: the interconnect layer pads maintain their metal film coating for optimal solder wettability and electrical connection, while the recessed area and insulating layer surface are protected by the underfill resin barrier. This localized differentiation allows simultaneous optimization of bonding and insulation.
Data Source
AI summary
A wiring board includes a single-layer insulating layer, and a single-layer interconnect layer embedded in the insulating layer, wherein an entirety of a first surface of the interconnect layer is exposed in a recessed position relative to a first surface of the insulating layer, and a second surface of the interconnect layer is partially exposed in a recessed position relative to a second surface of the insulating layer.