Wiring Board Impedance Control via Variable Line Width
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In electronic devices with exposed terminals, such as SSDs, the increased parasitic capacitance due to protection circuits like TVS diodes leads to impedance mismatch, resulting in increased insertion loss and decreased return loss during signal transmission.
Innovation Solution
A wiring board design with varying line widths and strategically removed reference voltage layers to manage impedance, specifically narrowing the line width at the connection point of capacitive components like TVS diodes and increasing it elsewhere to maintain consistent impedance across the wiring pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a protection circuit with capacitive component is added to protect against electrostatic discharge, then reliability against ESD is improved, but parasitic capacitance increases causing impedance mismatch
Solution Approach 1:
The patent applies local quality by making the line width variable rather than uniform. Specifically, the line width is set to be narrower at portions connecting to capacitive components (TVS diodes) and wider at other portions. This local variation in geometric properties compensates for the local increase in parasitic capacitance, maintaining consistent impedance throughout the wiring pattern while preserving ESD protection functionality.
2Reliability
If protection circuit is added to terminal, then electrostatic breakdown is prevented, but insertion loss increases and return loss decreases
Solution Approach 1:
The patent implements local quality by varying the line width along the wiring pattern based on the local capacitance requirements. The line width is narrowed at sections connected to capacitive components (TVS diodes) where parasitic capacitance is higher, and widened at other sections. This compensates for capacitance variations and maintains consistent impedance, thereby reducing insertion loss and improving return loss while preserving electrostatic protection.
Data Source
AI summary
A wiring board includes: a substrate having a first surface; a terminal disposed to the first surface of the substrate; a wiring pattern connected to the terminal on the first surface and configured to transmit a signal; and a reference voltage layer to which a reference voltage is configured to be applied, the reference voltage layer being disposed inside the substrate or to a second surface, which is opposite to the first surface, a line width of the wiring pattern in a wiring region including a portion connecting to a capacitive component being narrower than a line width of the wiring pattern at a portion other than the wiring region, the reference voltage layer being partially removed at a portion overlapping the wiring region when the substrate is viewed from above.