Multilayer Wiring Board Via Plating for Independent Thickness Control
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Solution Overview
Problem
The existing multilayer wiring boards face limitations in design freedom for the thickness of interconnect layers due to the need for simultaneous via hole filling and interconnect layer formation, which restricts the thickness to a predetermined value.
Innovation Solution
The wiring board design includes separate via interconnects and interconnect layers, with each having distinct seed and electrolytic plating layers, allowing independent thickness design and separate plating processes for filling and forming, enhancing design freedom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the conductor is formed on the upper surface of the insulating layer to a predetermined thickness or greater to fill via holes, then the via holes can be filled with the conductor, but the thickness of the interconnect layer cannot be designed with a large degree of freedom
Solution Approach 1:
The patent divides the conductor formation into two separate processes: (1) forming the interconnect layer on the insulating layer with a desired thickness, and (2) filling the via holes with conductor material in a subsequent process. This segmentation allows the interconnect layer thickness to be independently designed without being constrained by the via hole filling requirement, thereby resolving the contradiction between via hole filling completeness and thickness design freedom.
2Ease of manufacture
If the process of filling via holes and the process of forming the interconnect layer are performed simultaneously, then the via interconnects and interconnect are integrally formed, but the thickness of the interconnect layer is restricted to a predetermined value
Solution Approach 1:
The patent separates the integral formation process into two distinct stages: first forming the interconnect layer with the desired thickness, then separately filling the via holes. This allows the design freedom to be maintained while still achieving integral formation through coordinated processes, resolving the contradiction between ease of manufacture and thickness design freedom.
3Reliability
If the conductor thickness is increased to ensure via hole filling, then the via holes are properly filled, but the manufacturing flexibility and efficiency are reduced
Solution Approach 1:
By separating the interconnect layer formation from the via hole filling process, the patent enables independent optimization of each process. The interconnect layer can be formed with the minimum necessary thickness for electrical performance, while via hole filling is performed separately with appropriate conductor material, thereby improving both reliability and manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables independent control of interconnect layer thickness and reduces thickness variations, improving manufacturing flexibility and efficiency.
Implementation Method 1
a first electrolytic plating layer provided on the first seed layer
Implementation Method 2
a second electrolytic plating layer provided on the second seed layer
Data Source
AI summary
A wiring board includes a first interconnect layer, an insulating layer covering the first interconnect layer, a via interconnect penetrating the insulating layer, and a second interconnect layer provided on an upper surface of the insulating layer and electrically connected to the first interconnect layer through the via interconnect. The via interconnect includes a first seed layer that covers an inner wall surface of a via hole penetrating the insulating layer, and an upper surface of the first interconnect layer exposed inside the via hole, and a first electrolytic plating layer provided on the first seed layer. The second interconnect layer includes a second seed layer provided on the upper surface of the insulating layer and on an upper surface of the first electrolytic plating layer, and a second electrolytic plating layer provided on the second seed layer.