Wiring Data Correction for IC Positional Deviations
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Solution Overview
Problem
Existing methods for generating wiring data in chip-first type systems and wafer level packages struggle to efficiently cope with arrangement errors of integrated circuits, leading to connection failures in redistribution layers, especially when connection destination electrodes partially overlap with semiconductor chips.
Innovation Solution
A wiring data generation apparatus and method that includes design, partial, and corrected wiring data generation units, which acquire and adjust wiring data to connect element electrodes and connection destination electrodes, allowing for efficient generation and correction of wiring patterns to account for positional deviations and overlapping configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wiring data is generated by redesigning the wiring pattern from the beginning to cope with IC arrangement errors, then connection reliability is improved, but calculation load and time consumption increase significantly
Solution Approach 1:
The patent performs preliminary actions by pre-calculating arrangement errors for multiple ICs before exposure, and pre-generating corrected wiring data that accounts for these errors. The system prepares compensation information in advance that can be applied during exposure without time-consuming real-time calculations, thus improving connection reliability while reducing actual exposure time.
Solution Approach 2:
The patent implements a dynamic wiring data generation system that automatically adjusts wiring patterns based on detected arrangement errors. The system dynamically modifies wiring data to connect electrodes despite positional deviations, enabling adaptive compensation without manual redesign while maintaining connection reliability.
2Measurement precision
If fine adjustment of overlapping exposure is performed to cope with arrangement errors, then positioning accuracy is improved, but the measure is insufficient for multiple ICs with different arrangement errors
Solution Approach 1:
The patent segments the compensation approach by treating each IC's arrangement error independently. The system detects and calculates arrangement errors for each IC separately, then generates specific compensation information for each IC's wiring connections. This segmented approach enables precise positioning for each IC while maintaining adaptability across multiple ICs with different error characteristics.
Solution Approach 2:
The patent changes the parameter of wiring data to account for arrangement errors. By modifying wiring coordinates and connection parameters based on detected positional deviations, the system adapts the wiring pattern to match actual IC positions, thereby achieving both positioning accuracy and adaptability to multiple ICs.
3Quantity of substance
If connection destination electrodes are arranged to overlap with semiconductor chips, then wiring density is improved, but existing wiring data generation methods cannot cope with this configuration
Solution Approach 1:
The patent extends the wiring space into a third dimension by allowing connection destination electrodes to be arranged in overlapping positions with semiconductor chips in the planar layout. The system generates wiring data that connects electrodes through vertical or three-dimensional pathways, enabling higher wiring density while accommodating the overlapping configuration through spatial dimensionality changes.
Data Source
AI summary
A design wiring data acquisition unit acquires design wiring data indicating design wiring for connecting element electrodes at design positions on a substrate and connection destination electrodes to each other. A partial wiring data generation unit generates partial wiring data indicating partial wiring obtained by deleting peripheral portions of the design positions of the element electrodes in the design wiring. An actual position data acquisition unit acquires actual position data indicating actual positions of the element electrodes on the substrate. A corrected wiring data generation unit generates corrected wiring data indicating corrected wiring that connects the partial wiring and the element electrodes at the actual positions to each other.