Wiring Structure With Differential Via Surface Roughness
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Solution Overview
Problem
The increasing number of input/output connections in semiconductor chips leads to larger and thicker semiconductor substrates, resulting in decreased yield and warpage issues during manufacturing, which complicates the production of semiconductor packages with enhanced electrical performance and additional functions.
Innovation Solution
A wiring structure with a conductive through via that extends through multiple dielectric and circuit layers, where the surface roughness of the circuit layers in contact with the via is greater than those not in contact, allowing for improved electrical connectivity and reduced substrate thickness, combined with a manufacturing method involving the attachment of upper and lower conductive structures, removal of stacking portions, and formation of accommodating holes for the via.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of I/O connections is increased, then the electrical performance and functions are improved, but the substrate size and thickness increase leading to decreased yield and warpage
Solution Approach 1:
The patent transitions from planar circuit expansion to three-dimensional stacked conductive structures. By stacking multiple conductive structures vertically and connecting them through conductive through vias, the design achieves high-density I/O connections in the vertical dimension while maintaining a compact substrate footprint, thereby improving electrical performance without increasing substrate size and yield
Solution Approach 2:
The patent implements nested conductive structures where inner conductive structures are positioned within outer conductive structures. This nested arrangement allows multiple circuit layers to be integrated in a compact vertical space, enabling high-density connections without proportionally increasing the overall substrate area, thus maintaining yield while achieving enhanced I/O capability
2Adaptability or versatility
If the number of I/O connections is increased, then additional functions are achieved, but the substrate thickness increases causing warpage
Solution Approach 1:
The patent uses vertical stacking to achieve additional functions through layered conductive structures connected by through vias. This vertical integration provides multiple functional layers within a controlled thickness, avoiding the warpage issues that would result from lateral expansion or excessive thickness accumulation
Solution Approach 2:
The patent applies different surface roughness characteristics to different portions of circuit layers. Specifically, the first portion in contact with conductive through vias has greater surface roughness to enhance adhesion and electrical contact, while the second portion has lower surface roughness. This localized quality differentiation optimizes both electrical performance and structural integrity without requiring increased substrate thickness
3Quantity of substance
If the substrate size is increased to accommodate more I/O connections, then more connections are achieved, but the manufacturing yield decreases
Solution Approach 1:
The patent achieves a high quantity of connections by stacking conductive structures vertically and interconnecting them through conductive through vias. This three-dimensional approach packs more connections into a smaller substrate area, maintaining consistent manufacturing dimensions and process control, thereby preserving manufacturing yield while increasing connection density
Data Source
AI summary
A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers and a plurality of circuit layers in contact with the dielectric layers. The conductive through via extends through at least a portion of the conductive structure. At least one of the circuit layers includes a first portion in contact with the conductive through via and a second portion in contact with the dielectric layer. A surface roughness of the first portion of the circuit layer is greater than a surface roughness of the second portion of the circuit layer.