Lower Wiring Layer Silicide Capping for Resistance Increase

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Solution Overview

Problem

As integrated circuit devices have been downscaled, there is a need for a low-resistance metal wiring layer with improved reliability due to reduced line widths and pitches, which existing technologies have not adequately addressed.

Innovation Solution

The integration of a lower conductive barrier film surrounding the lower wiring layer, combined with a first and second metal silicide capping layer, enhances the reliability of the metal wiring layer by protecting it from physical deterioration during the formation of contact holes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If line widths and pitches of metal wiring layers are reduced to achieve device downsaling, then device integration density is improved, but wiring layer reliability deteriorates due to increased resistance and susceptibility to physical deterioration

Engineering Contradiction:
Improveline widthVSAvoidwiring layer reliability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by forming protective capping layers (conductive barrier film and metal silicide capping layer) on the lower wiring layer before subsequent processing steps. These layers are prepared in advance to prevent physical deterioration during contact hole formation and other manufacturing processes, thereby maintaining wiring layer reliability despite reduced dimensions.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements beforehand cushioning by introducing protective layers that cushion and protect the lower wiring layer from mechanical damage. The conductive barrier film and metal silicide capping layer act as protective cushions that prevent direct exposure of the wiring layer to harmful processes, thus maintaining reliability in downscaled devices.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If protective layers are added to protect the lower wiring layer, then wiring layer reliability is improved, but device complexity increases

Engineering Contradiction:
Improvewiring layer reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by designing protective layers that perform multiple functions simultaneously. The conductive barrier film provides both mechanical protection and electrical barrier functions, while the metal silicide capping layer offers both protection and low-resistance conduction. This multi-functionality reduces the need for additional separate protective structures, thereby limiting complexity increase.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses composite materials by combining different metal layers with distinct properties. The lower wiring layer (first metal) is combined with a conductive barrier film (second metal) and a metal silicide capping layer, creating a composite structure that leverages the advantages of each material to provide both protection and electrical performance without requiring overly complex single-material solutions.

Inventive Principle:
Principle #40Composite materials

Data Source

PatentUS10438891B2Integrated circuit device
Publication Date: 2019.10.08 SAMSUNG ELECTRONICS CO LTD
  • US10438891B2 patent drawing
  • US10438891B2 patent drawing
  • US10438891B2 patent drawing

AI summary

An integrated circuit device includes an insulating film on a substrate, a lower wiring layer penetrating at least a portion of the insulating film, the lower wiring layer including a first metal, a lower conductive barrier film surrounding a bottom surface and a sidewall of the lower wiring layer, the lower conductive barrier film including a second metal different from the first metal, a first metal silicide capping layer covering a top surface of the lower wiring layer, the first metal silicide capping layer including the first metal, and a second metal silicide capping layer contacting the first metal silicide capping layer and disposed on the lower conductive barrier film, the second metal silicide capping layer including the second metal.