3D Memory Wiring Line Structure Merging Gate Layers
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Solution Overview
Problem
The challenge in developing a three-dimensional memory device is to increase integration density while maintaining efficient voltage transfer and reducing the thickness and cost of the device, as existing two-dimensional memory devices face limitations in scaling and wiring complexity.
Innovation Solution
A three-dimensional memory device structure is implemented with channel structures extending vertically, surrounded by gate lines and select lines, and a wiring line stack at the same layer as the gate lines, allowing for efficient voltage transfer and reduced thickness through shared processing steps and layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional wiring layers are added to transfer operation voltages and block select signals, then voltage transfer efficiency is improved, but device thickness and manufacturing cost increase
Solution Approach 1:
The patent merges the wiring line layer with the gate line layer, allowing both operation voltages and block select signals to be transferred through the same physical layer. This combining of functions into a single layer eliminates the need for separate additional wiring layers, thereby maintaining voltage transfer efficiency while reducing device thickness.
Solution Approach 2:
The gate line layer is designed to serve multiple functions: it acts as both the gate electrode structure and the wiring line for signal transfer. This multi-functional design allows the same layer to handle both block select signals and operation voltages, eliminating the need for dedicated separate wiring layers and reducing overall device thickness.
2Reliability
If additional wiring layers are added to transfer operation voltages and block select signals, then voltage transfer efficiency is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the wiring line layer with the gate line layer, allowing both operation voltages and block select signals to be transferred through the same physical layer. This combining of functions into a single layer eliminates the need for separate additional wiring layers, thereby maintaining voltage transfer efficiency while reducing device thickness.
Solution Approach 2:
The gate line layer is designed to serve multiple functions: it acts as both the gate electrode structure and the wiring line for signal transfer. This multi-functional design allows the same layer to handle both block select signals and operation voltages, eliminating the need for dedicated separate wiring layers and reducing overall device thickness.
3Ease of operation
If more wiring layers are used, then signal transfer capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the wiring line layer with the gate line layer, allowing both operation voltages and block select signals to be transferred through the same physical layer. This combining of functions into a single layer eliminates the need for separate additional wiring layers, thereby maintaining voltage transfer efficiency while reducing device thickness.
Solution Approach 2:
The gate line layer is designed to serve multiple functions: it acts as both the gate electrode structure and the wiring line for signal transfer. This multi-functional design allows the same layer to handle both block select signals and operation voltages, eliminating the need for dedicated separate wiring layers and reducing overall device thickness.
Data Source
AI summary
A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.