Wiring Pattern Data Generation for Semiconductor Electron Beam Exposure
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Solution Overview
Problem
The electron beam exposure method for generating wiring patterns in semiconductor integrated circuits has a low throughput due to the need for individual exposure of varied shaped beams, which is inefficient for complex wiring patterns.
Innovation Solution
A method is developed to generate wiring pattern data by connecting basic block patterns with track patterns at a prescribed pitch, cutting away terminal ends of unused track patterns, and creating block pattern identifiers for efficient electron beam exposure using a block mask, allowing for collective exposure of patterns in a prescribed area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If variable shaped beam (VSB) lithography is used to expose the resist film, then patterns can be transferred with flexibility in shape, but the throughput is low due to a large number of exposure times
Solution Approach 1:
The patent segments the resist film exposure area into multiple prescribed areas (e.g., rectangular areas of 1 μm side), and uses separate block masks for each area. This allows parallel processing of different pattern regions, significantly increasing throughput while maintaining the ability to create various pattern shapes through the use of different block mask patterns for each segmented area.
2Productivity
If character projection (CP) method with block mask is used to improve throughput, then patterns in a prescribed area can be formed collectively at one-time exposure, but the block mask pattern must be precisely designed to avoid unwanted intersections
Solution Approach 1:
The patent performs preliminary actions by: (1) dividing the wiring pattern into multiple prescribed areas before block mask creation, (2) designing block mask patterns in advance with predetermined aperture shapes and positions, and (3) pre-assigning specific block masks to specific prescribed areas. This preliminary organization eliminates the need for complex real-time adjustments and ensures that block mask patterns do not create unwanted intersections, simplifying the overall design process while maintaining high throughput.
3Productivity
If block mask patterns are used for collective exposure, then the number of exposure times is reduced, but the wiring pattern data must be precisely organized with block pattern identifiers and layout positions
Solution Approach 1:
The patent creates simplified copies or representations of the wiring pattern data in the form of block mask patterns. Instead of handling complex continuous wiring patterns, the system uses discrete block mask patterns (aperture shapes) that replicate the essential exposure requirements. Each block mask pattern is assigned a unique identifier and layout position, creating a simplified data structure that is much easier to organize and process while maintaining the ability to reproduce the desired wiring patterns through collective exposure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the throughput of electron beam exposure for wiring patterns by enabling collective exposure and reducing the number of exposure times, improving the efficiency of the semiconductor manufacturing process.
Implementation Method 1
the aperture shape of a block mask (hereafter referred to as block mask pattern) is transferred to the resist film by irradiating the resist film with an electron beam through the block mask
Data Source
AI summary
A method includes connecting in a wiring area a plurality of basic block patterns which include a plurality of track patterns extending to one direction and being disposed at a prescribed pitch in an intersection direction intersecting the one direction to generate a plurality of parallel wiring patterns, each of which includes the track patterns connected together; generating a wiring route running on a track pattern; cutting away a track pattern terminal end, on which no wiring route runs, out of track pattern terminal ends of a track pattern including a route end of the wiring route and an adjacent track pattern connected to a track pattern start end of the track pattern concerned; and generating a wiring pattern data including a block pattern identifier corresponding to a basic block pattern out of the basic block patterns in the wiring area and a layout position of the basic block pattern.