Wiring Section Connection Testing Before Semiconductor Chip Mounting
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Solution Overview
Problem
The existing methods for manufacturing mounting substrates with semiconductor chips face challenges in conducting reliable connection tests for individual wiring sections before chip mounting, leading to potential malfunctions and increased costs due to the need for disposing of high-cost chips after they are mounted on malfunctioning substrates.
Innovation Solution
A method involving forming wiring sections by electrolytic plating on a supporting substrate, performing connection tests using conductive patterns, and then mounting the semiconductor chip, followed by removing the supporting substrate to ensure high reliability and efficiency in the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection test is performed after semiconductor chip mounting, then the manufacturing process can be completed, but the reliability of wiring sections cannot be verified before chip mounting leading to potential malfunctions and increased costs
Solution Approach 1:
The patent performs the connection test (SOT) on wiring sections before mounting the semiconductor chip. The test is conducted on the supporting substrate while wiring sections are electrically connected to the power supply layer, allowing verification of wiring reliability in advance. This preliminary testing prevents mounting chips on defective substrates, avoiding costly rework and improving overall manufacturing reliability.
2Ease of manufacture
If connection test is performed after semiconductor chip mounting, then the manufacturing process is simplified, but the cost increases due to disposal of malfunctioning chips
Solution Approach 1:
The connection test is performed before chip mounting, allowing defective substrates to be identified and discarded before the expensive chip is attached. This preliminary quality check prevents waste of high-cost semiconductor chips by ensuring only functional wiring sections receive chips, thereby reducing material loss while maintaining manufacturing simplicity.
3Ease of manufacture
If wiring sections are electrically connected to power supply layer, then electrolytic plating can be performed, but connection test cannot be conducted on individual wiring sections
Solution Approach 1:
The patent segments the power supply layer into multiple isolated conductive patterns after wiring section formation. By patterning the power supply layer to create separate conductive regions, each wiring section can be individually tested for electrical continuity and connectivity. This segmentation enables detection and measurement of individual wiring sections while maintaining the ease of manufacturing through standard electrolytic plating processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reliable connection testing before chip mounting, reducing the likelihood of manufacturing errors and increasing the yield of substrates with high-reliability wiring sections connected to semiconductor chips, thereby minimizing the risk of costly chip disposal and enhancing manufacturing efficiency.
Implementation Method 1
forming a wiring section by electrolytic plating on a first face of a supporting substrate which is made of an insulating material, by supplying electric power from a first power supply layer through a via plug piercing through the supporting substrate
Data Source
AI summary
A method for manufacturing a mounting substrate on which a semiconductor chip is mounted includes: forming a wiring section by electrolytic plating on a first face of a supporting substrate which is made of an insulating material, by supplying electric power from a first power supply layer through a via plug piercing through the supporting substrate, the first power supply layer being formed on a second face of the supporting substrate; performig patterning on the first power supply layer so as to form a first conductive pattern which is connected to the wiring section through the via plug; performing a connection test of the wiring section by using the conductive pattern; mounting the semiconductor chip on the wiring section; and removing the supporting substrate.