Semiconductor Wiring Stack Alignment for Fine Dense Interconnects
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices face challenges in achieving high yield ratios and forming fine, highly dense wiring layers due to issues such as the need for multiple redistribution layers, which can lead to productivity decline and insulation reliability problems, especially when solder deformation occurs and adjacent bumps are contacted.
Innovation Solution
A method involving the formation of conductive layers within grooves in organic insulating layers, with barrier metal films to prevent diffusion, and precise alignment and joining of these layers to create a fine and highly dense wiring structure, ensuring high yield and reliable insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple redistribution layers are used to match bump diameters, then connection precision is improved, but device complexity and manufacturing time increase
Solution Approach 1:
The patent extracts and eliminates the intermediate redistribution layers from the conventional multi-layer structure. Instead of using multiple redistribution layers to gradually transform bump diameters, the invention directly connects bumps of different diameters through a simplified structure, removing the complex intermediate transformation layers while maintaining connection precision.
Solution Approach 2:
The patent inverts the conventional approach by not trying to make all bumps the same size through redistribution layers. Instead, it accepts and utilizes the different bump diameters directly, connecting small-diameter bumps to large-diameter pads without forcing size uniformity, thereby simplifying the overall structure.
2Manufacturing precision
If multiple redistribution layers are used to match bump diameters, then connection precision is improved, but productivity deteriorates
Solution Approach 1:
The patent removes the time-consuming redistribution layer formation process from the manufacturing flow. By eliminating these intermediate layers, the manufacturing process is significantly shortened, improving productivity while maintaining the necessary connection precision through direct bump-to-pad alignment.
3Strength
If solder is melted by heating and pressurization to stack chips, then connection strength is improved, but solder deformation occurs causing yield ratio deterioration
Solution Approach 1:
The patent changes the connection method from thermal-mechanical solder bonding to direct mechanical pressing. By eliminating the heating and melting process, the invention avoids solder deformation while still achieving sufficient connection strength through direct pressure application, thereby improving yield ratio.
4Quantity of substance
If distance between solder and solder is shortened for high density, then quantity of connections is improved, but insulation reliability deteriorates
Solution Approach 1:
The patent introduces an organic insulating layer as an intermediary between adjacent conductive bumps. This insulating layer prevents electrical shorting between closely spaced bumps while allowing the bumps to be positioned close together for high-density connections, thereby maintaining both connection density and insulation reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the manufacturing of semiconductor devices with fine and highly dense wiring layers at a high yield ratio, preventing insulation deterioration and ensuring reliable connections between semiconductor chips and wafers or support substrates.
Implementation Method 1
heating and pressurization to stack the semiconductor chips
Implementation Method 2
heating and pressurization to stack the semiconductor chips
Implementation Method 3
forming a conductive layer formed from a conductive material on the first organic insulating layer
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming a first organic insulating layer including a groove; forming a conductive layer formed from a conductive material on the first organic insulating layer to fill the groove with the conductive material; removing a portion of the conductive layer on the first organic insulating layer, and acquiring a first wiring structure including a first wiring layer and the first organic insulating layer; providing a second wiring structure including a second organic insulating layer and a second wiring layer; and stacking the first wiring structure and the second wiring structure by pressurizing them while performing alignment so that the first wiring layer and the second wiring layer correspond to each other. In the stacking, the first wiring layer and the second wiring layer are joined, and the first organic insulating layer and the second organic insulating layer are joined to each other.