Wiring Structure Using 2D Layered Material for Low Resistance
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Solution Overview
Problem
As the line width and thickness of metal wiring in semiconductor devices are reduced, the electrical resistance increases, approaching a physical limit that hampers further improvement in semiconductor device performance, particularly in high-density and high-performance applications.
Innovation Solution
The introduction of a two-dimensional layered material layer, such as TMDCs-based materials or hexagonal boron nitride, between conductive material layers to act as a grain expansion layer, reducing the resistance by increasing the grain size of the second conductive material layer and maintaining or reducing the overall thickness of the wiring structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the line width and thickness of metal wiring are reduced, then the quantity of semiconductor chips integrated per wafer increases and line capacitance decreases, but the electrical resistance of the wiring increases
Solution Approach 1:
The patent applies composite materials by combining a two-dimensional layered material (such as graphene, h-BN, or MoS2) with traditional metal wiring materials. This composite structure leverages the high electrical conductivity and atomically thin profile of two-dimensional materials to reduce wiring resistance while maintaining the reduced dimensions required for high-density integration. The two-dimensional layered material forms a distinct layer within the wiring structure, creating a composite conductive path that overcomes the resistance limitations of pure metal wiring at scaled dimensions.
Solution Approach 2:
The patent changes the physical and chemical parameters of the wiring structure by introducing two-dimensional materials with unique electronic properties. These materials exhibit different electrical conductivity, carrier mobility, and atomic structure compared to conventional metals. By selecting specific two-dimensional materials and controlling their thickness (typically single or few layers), the wiring resistance parameter is optimized for reduced-line-width applications while maintaining compatibility with existing semiconductor manufacturing processes.
2Speed
If the line width and thickness of metal wiring are reduced, then the speed of signals passing through the wiring increases, but the electrical resistance increases to a point that frustrates semiconductor device operations
Solution Approach 1:
The patent employs composite materials consisting of two-dimensional layered materials integrated with metal wiring. The two-dimensional material layer provides a low-resistance conduction path that compensates for the increased resistance inherent in reduced-dimension metal wiring. This composite structure maintains high signal speed by reducing the overall resistance without requiring further reduction in line width or thickness, thus breaking the trade-off between speed improvement and resistance increase.
Solution Approach 2:
The two-dimensional layered material acts as an intermediary layer within the wiring structure, mediating between the metal wiring layers. This intermediate layer facilitates charge transport and reduces contact resistance at interfaces, thereby lowering the overall wiring resistance while preserving the high signal speed achieved through reduced dimensions. The intermediary two-dimensional material effectively decouples the relationship between line width reduction and resistance increase.
3Speed
If the thickness of metal wiring is reduced, then the line capacitance decreases and signal speed increases, but the electrical resistance increases
Solution Approach 1:
The patent utilizes composite materials where a two-dimensional layered material is integrated into the wiring structure. This composite approach allows the wiring to maintain reduced thickness for low capacitance and high signal speed, while the two-dimensional material provides enhanced electrical conductivity to counteract the resistance increase. The synergistic combination enables simultaneous optimization of speed and resistance parameters that cannot be achieved with metal wiring alone.
Data Source
AI summary
A wiring structure may include at least two conductive material layers and a two-dimensional layered material layer in an interface between the at least two conductive material layers. The two-dimensional layered material layer may include a grain expander layer which causes grain size of a conductive material layer which is on the two-dimensional layered material layer to be increased. Increased grain size may result in resistance of the second conductive material layer to be reduced. As a result, the total resistance of the wiring structure may be reduced. The two-dimensional layered material layer may contribute to reducing a total thickness of the wiring structure. Thus, a low-resistance and high-performance wiring structure without an increase in a thickness thereof may be implemented.