Wiring Substrate Ball Pad Design for Board Level Reliability
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Solution Overview
Problem
Three-dimensionally stacked semiconductor packages face issues with board level reliability due to cracks occurring at the junctions of solder balls, especially at the corners, during tests like drop impact and temperature cycle, leading to decreased yield and bonding reliability.
Innovation Solution
The wiring substrate design includes varying the surface areas of ball pads, with increased surface areas at corners and dummy ball pads to absorb mechanical stresses, and strategically formed solder balls to inhibit cracks and enhance bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform ball pads are used on the wiring substrate, then manufacturing is simplified, but cracks occur at solder ball junctions during board level reliability tests due to warp-induced distance differences
Solution Approach 1:
The patent applies local quality by varying the surface areas of ball pads based on their specific locations on the wiring substrate. Corner ball pads are designed with larger surface areas to compensate for greater warp-induced stress and distance differences, while central ball pads have smaller surface areas. This location-specific differentiation resolves the contradiction by maintaining manufacturing feasibility through a systematic design rule while significantly improving solder ball junction reliability under warp conditions.
2Reliability
If larger ball pad surface areas are used to compensate for warp, then bonding reliability improves, but the distance difference between central and peripheral ball pads increases
Solution Approach 1:
The patent applies parameter changes by systematically varying the surface area parameter of ball pads according to their position on the wiring substrate. The surface area is increased for peripheral and corner ball pads to compensate for warp-induced distance differences, while maintaining smaller areas for central ball pads. This controlled parameter variation resolves the contradiction by improving bonding reliability at critical locations without uniformly increasing all dimensions, thereby managing the distance difference effect strategically.
3Productivity
If three-dimensionally stacked semiconductor packages are used to achieve high integration, then capacity increases, but yield decreases due to crack formation during board level reliability tests
Solution Approach 1:
The patent applies local quality by differentiating ball pad designs based on their specific positions within the stacked package structure. Corner and peripheral ball pads in the lower package are designed with larger surface areas to withstand greater mechanical stress during board level reliability tests, while central ball pads maintain smaller areas. This location-specific design resolves the contradiction by maintaining high integration capacity through three-dimensional stacking while significantly improving package yield by preventing crack formation at stress-prone locations.
Data Source
AI summary
A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.