Wiring Substrate Conductive Pattern Exposure Length for Flip-Chip Solder Control
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Solution Overview
Problem
In semiconductor devices with flip-chip bonded electronic components, the narrow intervals between conductive patterns on a wiring substrate can lead to short circuits due to excessive solder accumulation between adjacent bumps, as the existing bonding methods do not effectively manage the amount of brazing metal across varying pattern intervals.
Innovation Solution
The solution involves adjusting the exposure lengths of conductive patterns on a wiring substrate, with narrower intervals having shorter exposure lengths to reduce the amount of brazing metal applied, thereby preventing short circuits by ensuring sufficient spacing between solder accumulations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder powders are applied to whole exposed surfaces of conductive patterns, then electrical connection reliability is improved, but short circuit risk increases in narrow interval regions
Solution Approach 1:
The patent applies different exposure lengths to conductive patterns based on their local interval characteristics. Conductive patterns in narrow interval regions have shorter exposure lengths, while those in wide interval regions have longer exposure lengths. This local differentiation ensures reliable electrical connection in each region while preventing solder overflow and short circuits in narrow intervals.
Solution Approach 2:
The patent changes the exposure length parameter of conductive patterns according to the interval width. By adjusting this geometric parameter locally, the amount of solder powder applied is controlled to match the available space, preventing both insufficient connection and excessive solder accumulation that could cause short circuits.
2Ease of manufacture
If equal exposure lengths are used for all conductive patterns, then manufacturing simplicity is maintained, but solder accumulation control deteriorates in narrow intervals
Solution Approach 1:
Instead of uniform exposure lengths, the patent implements local quality by varying exposure lengths according to the specific interval characteristics of each conductive pattern region. This allows precise control of solder accumulation in narrow intervals while maintaining adequate exposure in wide intervals.
Solution Approach 2:
The exposure lengths are predetermined and designed into the conductive patterns before the soldering process. This preliminary design of varying exposure lengths pre-prevents potential solder overflow issues in narrow intervals, eliminating the need for complex real-time control during manufacturing.
3Strength
If conductive patterns have wide exposure surfaces, then bonding strength is improved, but solder overflow between adjacent patterns increases
Solution Approach 1:
The patent applies different exposure lengths to different conductive patterns based on their local environment. Patterns in narrow intervals have shorter exposure lengths to prevent solder overflow, while patterns in wide intervals can have longer exposure lengths to ensure adequate bonding strength.
Solution Approach 2:
The exposure length parameter is varied locally to optimize both bonding strength and solder overflow prevention. By changing this parameter according to interval width, the patent achieves adequate bonding in all regions while preventing harmful solder accumulation in narrow intervals.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable electrical connections by controlling the amount of brazing metal, preventing short circuits at narrow intervals while maintaining strong bonding at wider intervals, thus enhancing the reliability of the flip-chip bonding process.
Implementation Method 1
solder powders are applied to whole exposed surfaces of the conductive patterns 106, 106, then the solder powders are fused to cover the wide portion 106a of the conductive pattern 106 with fused solder
Implementation Method 2
the solder 108 covering whole exposed surfaces of the conductive patterns 106 gathers around peripheral surfaces of the bumps 104 respectively due to a surface tension
Data Source
AI summary
A wiring substrate on which an electronic component is flip-chip bonded, including a substrate main body, a solder resist which is formed on the substrate main body and having an opening, and a plurality of conductive pattern formed on the substrate main body, including exposure surfaces exposed from the opening of the solder resist. The conductive patterns include, a narrow interval group, a wide interval group, an interval between the adjacent conductive patterns belonging to the narrow interval group is narrower than an interval between the adjacent conductive patterns belonging to the wide interval group, an exposure length of the conductive patterns of the narrow interval group is shorter than an exposure length of the conductive patterns of the wide interval group.