Semiconductor Wiring Substrate Layout for Dense Low-Crosstalk Routing
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Solution Overview
Problem
Existing semiconductor designs face challenges in achieving high routing flexibility and signal integrity, particularly with the increasing demands of high-bandwidth memory applications.
Innovation Solution
A semiconductor wiring substrate design featuring alternately arranged signal and ground traces with wider ground traces, a redistribution layer, and a power/ground layout, which allows for increased channel width and improved signal transmission without increasing the spacing between solder bumps, enhancing routing flexibility and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the channel width is increased to improve routing flexibility and signal integrity, then the spacing between solder bumps must be increased, but this increases the overall device area and reduces integration density
Solution Approach 1:
The patent transitions from a traditional planar layout to a 3D stacked architecture with multiple circuit layers (first circuit layer, second circuit layer, third circuit layer) separated by dielectric layers. This vertical dimensionality allows signal traces to be routed across multiple layers, effectively increasing routing flexibility without requiring larger horizontal spacing between solder bumps on the same layer
Solution Approach 2:
The patent divides the circuit into multiple segmented layers with dedicated functions: signal transmission layers, power/ground layers, and redistribution layers. Each layer is optimized for specific purposes, allowing independent optimization of signal integrity and routing without compromising overall device area
2Reliability
If wider ground traces are used to reduce crosstalk and improve signal quality, then the channel width increases, but this reduces the number of channels that can be packed in a given area
Solution Approach 1:
The patent uses multiple vertical layers to accommodate both wide ground traces for signal integrity and multiple channels for high density. By distributing channels across different Z-height layers, the system achieves both wide traces on each layer and high overall channel count without horizontal spacing constraints
Solution Approach 2:
Different layers are assigned different local qualities: signal layers have optimized trace widths for low crosstalk, power/ground layers have wider traces for low impedance, and redistribution layers have optimized patterns for bump alignment. This local optimization allows each layer to be tuned for its specific function
3Reliability
If the spacing between solder bumps is increased to accommodate wider channels, then signal integrity improves, but the land pattern area increases and manufacturing cost rises
Solution Approach 1:
The patent achieves signal integrity through vertical layering rather than horizontal spacing. Multiple circuit layers with controlled impedance and proper grounding can be implemented with standard bump pitch, avoiding the need for larger land patterns and reducing manufacturing costs
Data Source
AI summary
A semiconductor wiring substrate includes at least one circuit layer, at least one dielectric layer and a redistribution layer. The at least one circuit layer includes multiple signal traces and multiple ground traces alternately arranged on the at least one circuit layer, and has a channel width in a direction. The at least one dielectric layer is between the at least one circuit layer. The redistribution layer is above the at least one circuit layer, allows a first solder bump and a second solder bump to be placed, and includes a first metal contact and a second metal contact. The first solder bump and the second solder bump connect the at least one circuit layer through the first metal contact and the second metal contact, respectively. The channel width is greater than spacing between the first solder bump and the second solder bump in the direction.