Wiring Substrate Identification Mark Contrast via Recessed Solder Resist
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Solution Overview
Problem
Existing wiring substrates have limited recognition of identification marks, which are crucial for positioning and defect analysis after singulation, and current methods do not provide sufficient contrast and recognizability.
Innovation Solution
The proposed solution involves forming identification marks on the wiring substrate using via wirings, a conductive pattern, and a protective insulation layer, where the via wirings and conductive pattern are made from the same material, and the recesses defined by the via wirings are filled with a solder resist layer that is thicker over the via wirings than the conductive pattern, creating a recognizable shape with increased contrast.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If identification marks are formed by boring through holes and forming plating layers, then the marks can be created on the wiring substrate, but the recognition and contrast of the marks are insufficient
Solution Approach 1:
The patent applies local quality by creating recesses in the solder resist layer at specific locations corresponding to via holes, while maintaining a different thickness of solder resist over conductive patterns. This local variation in solder resist thickness creates optical contrast that enhances mark recognition without affecting the overall substrate structure
Solution Approach 2:
The patent transitions from a two-dimensional planar mark to a three-dimensional structure by forming recesses in the solder resist layer. These recesses create height differences and optical depth that enhance contrast and recognizability when viewed under magnification, adding a vertical dimension to the identification mark
2Measurement precision
If the protective insulation layer thickness is increased to improve mark visibility, then contrast is enhanced, but the flatness of the substrate surface is compromised
Solution Approach 1:
The solder resist layer is applied with locally controlled thickness: thicker over via holes to form recesses that enhance contrast, and thinner over conductive patterns to maintain overall surface flatness. This selective thickness distribution achieves both visibility and flatness requirements simultaneously
Solution Approach 2:
The solder resist layer is applied excessively (thicker) only at specific locations where via holes are present, rather than uniformly across the entire substrate. This partial excessive action provides the needed contrast enhancement only where required for mark identification, while preserving flatness in other areas
Data Source
AI summary
A wiring substrate includes first through holes extending through an insulation layer, first via wirings formed in the first through holes, a conductive pattern connected to the first via wirings, recesses formed in the first via wirings, and a protective insulation layer covering the conductive pattern and the first via wirings. The first via wirings, the conductive pattern, the recesses, and the protective insulation layer form an identification mark identifiable as a particular shape including a character or a symbol. Each recess is defined by an upper surface of the corresponding first via wiring and includes a curved side wall and a bottom wall that is located at a lower position than an upper surface of the conductive pattern. The protective insulation layer is thicker over the first via wirings than over the conductive pattern.