Wiring Substrate High Aspect Ratio Plating
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Solution Overview
Problem
Existing methods for manufacturing printed wiring boards face challenges in forming wiring patterns with high aspect ratios and small widths, leading to potential defects such as short circuits and uneven thicknesses due to the use of thick plating resist and electrolytic plating processes.
Innovation Solution
A wiring substrate is manufactured by forming a seed layer on an insulating layer, followed by a plating resist and an electrolytic plating film with a thickness greater than the resist, and then polishing both to achieve precise, high-aspect-ratio wiring patterns with perpendicular sidewalls, reducing the risk of defects and ensuring uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick plating resist and electrolytic plating process are used to form wiring patterns, then the wiring patterns can be formed with sufficient thickness, but the aspect ratio becomes too high leading to short circuits and uneven thicknesses
Solution Approach 1:
The patent changes the critical parameter of plating resist thickness to a specific range (5-20 μm) and controls the electrolytic plating thickness to be 1.5-3 times the resist thickness. This parameter optimization ensures the aspect ratio remains within 2.0-4.0, preventing short circuits while maintaining sufficient wiring pattern thickness and uniformity.
Solution Approach 2:
The patent replaces the conventional thick plating resist approach with a thinner resist (5-20 μm) combined with controlled electrolytic plating. This substitution of the plating process parameters achieves the same wiring pattern formation without the harmful effects of excessively high aspect ratios, eliminating short circuits and uneven thicknesses.
2Productivity
If the wiring width is reduced to 5 μm or less to increase density, then the wiring substrate can achieve higher integration, but the aspect ratio increases making defect prevention difficult
Solution Approach 1:
The patent optimizes the plating resist thickness parameter to 5-20 μm and controls electrolytic plating thickness to maintain aspect ratio within 2.0-4.0. This allows wiring width to be reduced to 5 μm or less for higher density while preventing aspect ratio from becoming excessively high, thus maintaining manufacturing precision and defect prevention capability.
3Productivity
If the distance between adjacent wirings is reduced to 7 μm or less to increase integration, then the wiring substrate achieves higher density, but the risk of short circuits increases
Solution Approach 1:
The patent controls the plating resist thickness to 5-20 μm and electrolytic plating thickness to maintain aspect ratio within 2.0-4.0. This parameter control enables adjacent wirings to be positioned at 7 μm or less while preventing short circuits through proper aspect ratio management, thus achieving high density without compromising reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of wiring substrates with high connection reliability and improved high-frequency transmission characteristics by maintaining the integrity of wiring patterns with high aspect ratios and small widths, while preventing short circuits and ensuring uniform thickness.
Implementation Method 1
forming an electrolytic plating film on the seed layer
Data Source
AI summary
A wiring substrate includes an insulating layer, a first conductor layer formed on the insulating layer and including a first wiring and a second wiring formed adjacent to the first wiring, and a second conductor layer on the opposite side with respect to first conductor layer such that the insulating layer is covering the second conductor layer. The first conductor layer is formed such that each of the first wiring and the second wiring has an aspect ratio in the range of 2.0 to 4.0 and a wiring width of 5 μm or less and that the first wiring and the second wiring are separated by the distance of 7 μm or less, and the first conductor layer includes a seed layer formed on the insulating layer, and an electrolytic plating film formed on the seed layer.