Wiring Substrate Re-wiring Layer Seed and Plating Structure
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Solution Overview
Problem
The high technical hurdle and increased manufacturing cost associated with producing silicon interposers for mounting high-performance semiconductor chips on wiring substrates, due to the complexity and cost of forming through holes and fine wiring layers, restricts the manufacturing process and increases costs.
Innovation Solution
A method of manufacturing a wiring substrate that involves forming a base wiring substrate with multiple layers and via holes, using a semi-additive process with seed layers and metal plating, and anisotropic dry etching to create a re-wiring portion with fine wirings directly on the substrate, eliminating the need for a silicon interposer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a silicon interposer is used for mounting high-performance semiconductor chips, then pitch conversion and fine wiring connections are achieved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
The patent extracts and eliminates the silicon interposer component from the mounting structure. Instead of using a separate silicon interposer substrate, the invention directly forms fine wiring layers and via holes on the wiring substrate itself, removing the intermediate component while maintaining the pitch conversion function. This reduces manufacturing complexity by consolidating multiple processes into a single substrate fabrication process.
Solution Approach 2:
The invention merges the functions of the silicon interposer with the wiring substrate by directly forming the fine wiring layers and via holes on the wiring substrate. The pitch conversion function previously achieved through the interposer is now integrated into the substrate fabrication process itself, combining multiple discrete components and processes into a unified structure.
2Manufacturing precision
If through holes and penetrating electrodes are formed in silicon substrate by dry etching and electroplating, then fine wiring connections are achieved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive silicon substrate processing with a more cost-effective approach using organic insulating layers and conventional wiring substrate materials. The via holes are formed through the insulating layers using standard fabrication techniques rather than expensive silicon dry etching, and the wiring layers are formed using electroplating on copper foils instead of penetrating electrodes in silicon, significantly reducing material and processing costs while maintaining via hole precision.
3Productivity
If multi-layered wirings are advanced to achieve higher density, then connection density increases, but manufacturing complexity increases
Solution Approach 1:
The patent segments the wiring structure into distinct functional layers: base wiring layers for power and ground, intermediate wiring layers for signal routing, and fine wiring layers for pitch conversion. Each layer type has specific via hole connections to adjacent layers, creating a modular multi-layered structure that achieves high connection density while managing manufacturing complexity through systematic layer organization and standardized fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing complexity and cost by enabling the direct formation of fine wirings on the substrate, allowing for efficient pitch conversion of semiconductor chip connections without the need for a silicon interposer, thereby simplifying the mounting process and reducing overall costs.
Implementation Method 1
forming a metal plating layer in the second via hole and the opening portion of the plating resist by electroplating
Implementation Method 2
forming a re-wiring layer by removing the seed layer by anisotropic dry etching while using the metal plating layer as a mask
Data Source
AI summary
A wiring substrate includes, a base wiring substrate including a first wiring layer, a first insulating layer in which the first wiring layer is buried and a first via hole is formed under the first wiring layer, and a second wiring layer formed under the first insulating layer and connected to the first wiring layer through the first via hole, and a re-wiring portion including a second insulating layer formed on the base wiring substrate and having a second via hole formed on the first wiring layer, and a re-wiring layer formed on the second insulating layer and connected to the first wiring layer through the second via hole. The re-wiring layer is formed of a seed layer and a metal plating layer provided on the seed layer, and the seed layer is equal to or wider in width than the metal plating layer.