Wiring Substrate Seed Layer Sidewall Plating

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Solution Overview

Problem

The challenge is to form fine wiring layers on a wiring substrate with a line width of 10 μm or less with high reliability, as existing methods face issues with electrical short-circuits and transmission loss due to surface unevenness of insulating resin layers, which complicates the formation of narrow pitch wiring layers and adherence to semiconductor chips.

Innovation Solution

A wiring substrate is developed with a copper/tin alloy layer, a coupling agent layer, and a seed layer, where the seed layer is formed only on the sidewall of the via hole, and a metal plating layer is filled to contact the wiring layer, ensuring smooth surface adhesion and preventing residue formation during etching, thus maintaining the insulating resin layer's smoothness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the surface of the insulating resin layer is roughened to secure adhesion of the wiring layer, then adhesion is improved, but the wiring layer cannot be formed with fine line width (10 μm or less) with high reliability due to residue formation and electrical short-circuits

Engineering Contradiction:

Improveadhesion of wiring layerVSAvoidreliability of fine wiring layer formation

Core Design Contradiction:

StrengthVSReliability

Solution Approach 1:

The patent applies local quality by differentiating the surface treatment of the insulating resin layer: the wiring formation regions maintain smooth surfaces to prevent residue and ensure fine pattern integrity, while the via hole regions undergo roughening treatment to provide anchoring effect for adhesion. This selective local treatment resolves the contradiction between needing adhesion and avoiding electrical short-circuits in fine wiring layers.

Inventive Principle:

Principle #3Local quality

2Manufacturing precision

If the pitch of the wiring layer is narrowed to achieve finer wiring, then wiring density is improved, but residue occurs during seed layer etching causing electrical short-circuits

Engineering Contradiction:

Improvewiring pitchVSAvoidelectrical insulation between wiring layers

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent implements local quality by maintaining smooth surfaces of the insulating resin layer specifically in the wiring formation regions, while allowing roughening in via hole regions. This localized smooth surface prevents residue formation during seed layer etching, ensuring electrical insulation is maintained even when wiring pitch is narrowed to fine dimensions.

Inventive Principle:

Principle #3Local quality

3Strength

If the surface of the insulating resin layer is uneven, then adhesion is improved, but transmission loss of high frequency signals occurs in the wiring layer

Engineering Contradiction:

Improveadhesion of wiring layerVSAvoidtransmission loss of high frequency signal

Core Design Contradiction:

StrengthVSLoss of energy

Solution Approach 1:

The patent applies local quality by creating smooth surfaces of the insulating resin layer in the wiring formation regions, which are necessary for low transmission loss of high frequency signals. Meanwhile, the via hole regions maintain roughened surfaces for adhesion. This spatial differentiation allows the wiring layer to have both good adhesion through via holes and low transmission loss through smooth wiring surfaces.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the reliable formation of fine wiring layers with reduced electrical short-circuits and transmission loss, enabling the creation of high-performance semiconductor chip mounting substrates with improved adhesion and pattern integrity.

Implementation Method 1

a metal catalyst provided on only a sidewall of the first via hole; a seed layer provided on the metal catalyst and formed only on the sidewall of the first via hole

Methodology Applied

Scientific EffectElectroless plating: Catalysis

Implementation Method 2

a metal plating layer formed on the first copper/tin alloy layer and the seed layer and filled in the first via hole to contact the first wiring layer

Methodology Applied

Scientific EffectElectroplating: Electroplating

Data Source

PatentUS9232644B2Wiring substrate

Publication Date: 2016.01.05 SHINKO ELECTRIC IND CO LTD

AI summary

There is provided a wiring substrate. The wiring substrate includes: a first wiring layer; a first insulating layer on the first wiring layer; a first coupling agent layer on the first insulating layer; a first copper/tin alloy layer on the first coupling agent layer; a first via hole formed through the first copper/tin alloy layer, the first coupling agent layer, and the first insulating layer to reach the first wiring layer; a metal catalyst provided on only a sidewall of the first via hole; a seed layer provided on the metal catalyst and formed only on the sidewall of the first via hole; and a metal plating layer formed on the first copper/tin alloy layer and the seed layer and filled in the first via hole to contact the first wiring layer.