Wiring Substrate With Segmented Multi-Layer Resin For Narrow Pitch
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Solution Overview
Problem
Current semiconductor device manufacturing methods struggle to accommodate high-density connection terminals due to limitations in wiring layer miniaturization and mechanical strength of external connection pads, making it difficult to mount high-performance semiconductor chips with narrow-pitch connection terminals.
Innovation Solution
A wiring substrate is developed with a first multi-layer wiring layer formed using non-photosensitive resin via laser-formed via holes, and a second multi-layer wiring layer with a narrower pitch formed using photosensitive resin via photolithography, allowing for exposed external connection pads with improved mechanical strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a general buildup technique is used to manufacture the lower wiring substrate, then the manufacturing process is simple and reliable, but the wiring pitch cannot be reduced below 10 μm, limiting the ability to accommodate narrow-pitch connection terminals
Solution Approach 1:
The wiring substrate is divided into two distinct multi-layer wiring layers: a first multi-layer wiring layer manufactured by general buildup technique with larger wiring pitch, and a second multi-layer wiring layer manufactured by fine processing technique with narrower wiring pitch. This segmentation allows each layer to be optimized for its specific function without compromising the overall manufacturing simplicity.
Solution Approach 2:
The patent transitions from a single-planar wiring layer to a three-dimensional stacked structure with multiple wiring layers at different heights. The second multi-layer wiring layer is formed on top of the first, enabling narrow-pitch wirings to coexist with larger-pitch external connection pads in different spatial dimensions.
2Manufacturing precision
If external connection pads are formed from the same layer as fine wirings, then the wiring pitch can be reduced, but the mechanical strength of the external connection pads becomes insufficient
Solution Approach 1:
Different regions of the wiring substrate are assigned different functional qualities: the first multi-layer wiring layer provides mechanically strong external connection pads with larger wiring pitch, while the second multi-layer wiring layer provides fine-pitch wirings for high-density connections. Each region is optimized for its specific requirement without compromising the other.
Solution Approach 2:
The connection structures are segmented into two functional groups: external connection pads in the first multi-layer wiring layer that require mechanical strength, and internal fine wirings in the second multi-layer wiring layer that require narrow pitch. This segmentation allows each component to be independently optimized.
3Productivity
If the wiring pitch is reduced to accommodate high-density connection terminals, then more chips can be mounted, but the mechanical strength and reliability of the connection pads deteriorate
Solution Approach 1:
The patent uses vertical stacking to separate high-density wiring functions from high-strength connection functions. The second multi-layer wiring layer provides the narrow pitch needed for high-density chip mounting, while the first multi-layer wiring layer maintains mechanically robust external connection pads, thereby achieving both high productivity and high reliability.
Solution Approach 2:
Different areas of the substrate are given different wiring pitches according to their functional requirements: regions requiring high-density connections use the second multi-layer wiring layer with narrow pitch, while regions requiring strong mechanical connections use the first multi-layer wiring layer with larger pitch, ensuring both high mounting density and connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the mounting of high-performance semiconductor chips with narrow-pitch connection terminals and enhances the mechanical strength of external connection pads, improving the reliability of connections and accommodating higher density chip arrangements.
Implementation Method 1
a first via hole is formed in an insulating layer formed of a non-photosensitive resin by a laser
Implementation Method 2
an insulating layer including a second via hole is formed by patterning a photosensitive resin by means of photolithography
Data Source
AI summary
A wiring substrate includes a first multi-layer wiring layer including an insulating layer formed of a non-photosensitive resin, a plurality of external connection pads formed on an upper face side of the first multi-layer wiring layer, and a second multi-layer wiring layer formed on the first multi-layer wiring layer, the second multi-layer wiring layer including an insulating layer formed of a photosensitive resin, the second multi-layer wiring layer having a wiring pitch narrower than the wiring pitch of the first multi-layer wiring layer. The external connection pads are exposed from the insulating layer of the second multi-layer wiring layer.