Wiring Substrate Pad Layout for Two-Mask Mini-LED Routing

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Solution Overview

Problem

The current glass-based Mini-LED display technology faces high manufacturing costs and low product yield due to the complexity of the six-mask, double-layer copper process used in the Back Plane (BP) light board, which is inefficient and costly.

Innovation Solution

A wiring substrate design with a simplified manufacturing process that arranges functional units in an array, featuring a second pad group with even-numbered pads in a 2*N array, allowing routing wires to be set in the same layer without overlapping, reducing the number of mask processes to two.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a six-mask, double-layer copper process is used for the Back Plane light board, then routing wires can be formed with proper connectivity, but the manufacturing process becomes complex with low yield and high cost

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidprocess complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent merges the routing wire layers into a single layer instead of using two separate copper layers. By consolidating the routing wires into one layer with strategic pad group arrangements, the complex six-mask double-layer process is simplified to a more efficient single-layer process, reducing manufacturing steps while maintaining electrical connectivity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent segments the pad groups into first pad groups and second pad groups with specific arrangements (2*N array configuration). This segmentation allows routing wires to be organized in a systematic manner within a single layer, enabling proper connectivity without requiring multiple copper layers, thus simplifying the manufacturing process.

Inventive Principle:
Principle #1Segmentation

2Productivity

If a six-mask, double-layer copper process is used, then routing connectivity is achieved, but production cost increases and product yield decreases

Engineering Contradiction:
Improveproduct yieldVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

By combining multiple copper layers into a single routing wire layer, the patent reduces the number of manufacturing steps and mask processes required. This consolidation directly improves product yield by reducing process complexity and decreases production cost by eliminating redundant manufacturing operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the structural parameter of the routing wire arrangement from a two-layer configuration to a single-layer configuration. This parameter change fundamentally alters the manufacturing process, reducing the number of mask processes from six to two, thereby improving productivity and reducing costs.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If routing wires are arranged in multiple layers, then connectivity is achieved, but the manufacturing process requires more mask processes

Engineering Contradiction:
Improvenumber of mask processesVSAvoidrouting wire arrangement
Core Design Contradiction:
Device complexityVSEase of manufacture

Solution Approach 1:

The patent utilizes the vertical dimension (z-axis) by arranging pad groups in specific configurations (first pad groups and second pad groups at different positions) within a single layer. This dimensional arrangement allows routing wires to achieve proper connectivity without requiring additional layers, thereby reducing the number of mask processes from six to two.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250241102A1Wiring substrate, light-emitting substrate, and display apparatus
Publication Date: 2025.07.24 HEFEI BOE RUISHENG TECH CO LTD
  • US20250241102A1 patent drawing
  • US20250241102A1 patent drawing
  • US20250241102A1 patent drawing

AI summary

A wiring substrate includes a plurality of functional units arranged in an array. Each of the functional units includes: a plurality of first pad groups arranged along a first direction, and a second pad group located at a side of the plurality of the first pad groups along the second direction. The second pad group includes a plurality of channel pads and at least two functional pads, and a quantity of pads in the second pad group is even and the pads in the second pad group are arranged at intervals in a 2*N array. The plurality of channel pads are arranged at intervals along a same direction in a first line and are respectively connected one-to-one with a plurality of first pad groups of which a quantity is same as a quantity of the plurality of the channel pads.