Wiring Substrate Recessed Under-Bump Pad for Low-Resistance Packaging
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high performance, compact size, and low manufacturing cost while ensuring reliable electrical connections and structural stability.
Innovation Solution
A wiring substrate is designed with a protection layer, under-bump pads, a dielectric pattern, and a conductive pattern. The under-bump pads have a recess region filled by the dielectric pattern, and the conductive pattern includes a pad part and a via part that penetrates the dielectric pattern to connect with the under-bump pad, optimizing electrical connections and structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires or bumps are used to electrically connect semiconductor chip and PCB, then electrical connection is achieved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent extracts and eliminates the bonding wires or bumps from the electrical connection structure. Instead of using separate bonding components, the invention integrates the electrical connection function directly into the PCB through the conductive pattern that extends from the via part to the pad part, thereby reducing manufacturing complexity and cost while maintaining connection reliability
Solution Approach 2:
The invention merges multiple functions into a single integrated structure. The conductive pattern combines the via part (for vertical penetration and connection to under-bump pad) and pad part (for surface mounting) into one continuous conductive path, eliminating the need for separate bonding wires or bumps and simplifying the overall manufacturing process
2Volume of moving object
If compact size is achieved in semiconductor package, then device dimensions are reduced, but structural stability and resistance to external impacts deteriorate
Solution Approach 1:
The patent transitions from a two-dimensional surface connection to a three-dimensional integrated structure. The conductive pattern with via part penetrating through dielectric layers and connecting to under-bump pads creates vertical pathways, utilizing the third dimension to achieve compact horizontal footprint while maintaining robust structural connections that resist external impacts
3Ease of manufacture
If conventional conductive pattern design is used, then manufacturing is simpler, but electrical resistance and contact resistance are higher
Solution Approach 1:
The invention performs preliminary action by extending the conductive pattern from the via part through the dielectric layer to the pad part in advance, creating a continuous conductive path before final assembly. This pre-established connection reduces contact resistance at interfaces and ensures optimal electrical conductivity while maintaining manufacturing feasibility through standard PCB fabrication processes
Data Source
AI summary
A wiring substrate and semiconductor package including a protection layer, an under-bump pad including an upper part disposed on a top surface of the protection layer and a lower part penetrating the protection layer, a dielectric pattern disposed on the protection layer, and a conductive pattern disposed on the dielectric pattern. The lower part of the under-bump pad is exposed on a bottom surface of the protection layer, and the under-bump pad includes a recess region directed into a bottom surface of the under-bump pad from a top surface of the under-bump pad. The dielectric pattern covers a portion of the under-bump pad and fills the recess region. The conductive pattern includes a pad part disposed on a top surface of the dielectric pattern and a via part that vertically penetrates the dielectric pattern and is coupled to the top surface of the under-bump pad.