Wiring Substrate Via Hole Formation with Staged Desmear

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Solution Overview

Problem

Existing methods for manufacturing wiring substrates face challenges in efficiently forming via holes with different diameters and inter-pad distances, leading to issues like haloing and peeling of the insulating layer, especially when the inter-pad distance of second conductor pads is shorter.

Innovation Solution

A method involving the formation of first and second via holes with different diameters and inter-pad distances, followed by desmear treatments with varying processing times to prevent haloing and peeling, where the second via holes are formed after the first desmear treatment and have a shorter processing time to ensure proper adhesion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If via holes are formed with shorter inter-pad distances, then the wiring substrate can accommodate higher density connections, but haloing and peeling occur between the insulating layer and conductor pads

Engineering Contradiction:
Improveconnection densityVSAvoidadhesion integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies a desmear treatment before forming via holes to preliminarily clean the insulating layer surface and remove organic residues. This preliminary action prevents haloing and peeling that would occur during subsequent via hole formation, enabling reliable high-density connections without adhesion defects

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the parameters of the desmear treatment process, specifically using plasma treatment at controlled power levels (50-200W) and durations (1-10 minutes) to optimize the cleaning effect. By adjusting these parameters, the insulating layer is sufficiently cleaned to prevent haloing while maintaining its structural integrity for high-density via hole formation

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If desmear treatment processing time is extended, then residues are more thoroughly removed from via holes, but processing efficiency decreases

Engineering Contradiction:
Improveresidue removal completenessVSAvoidprocessing efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent optimizes the desmear treatment parameters by controlling plasma power (50-200W) and treatment duration (1-10 minutes). This parameter optimization achieves thorough residue removal from via holes while maintaining short processing times, thus balancing manufacturing precision with processing efficiency

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent uses periodic plasma treatment cycles with specific on/off timing to achieve effective residue removal. The periodic nature of plasma discharge allows sufficient cleaning action during active phases while limiting total exposure time, thereby maintaining both completeness of residue removal and processing efficiency

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20240237231A9Method for manufacturing wiring substrate
Publication Date: 2024.07.11 IBIDEN CO LTD
  • US20240237231A9 patent drawing
  • US20240237231A9 patent drawing
  • US20240237231A9 patent drawing

AI summary

A method for manufacturing a wiring substrate includes forming first conductor pads and second conductor pads having a shorter inter-pad distance than the first conductor pads, forming a second insulating layer covering the first conductor pads and the second conductor pads, forming first via holes exposing the first conductor pads, applying a first desmear treatment such that residues are removed from the first via holes, forming second via holes in the second insulating layer after the first desmear treatment such that the second via holes expose the second conductor pads, applying a second desmear treatment such that residues are removed from the second via holes, forming first via conductors in the first via holes such that the first via conductors are formed on the first conductor pads, and forming second via conductors in the second via holes such that the second via conductor are formed on the second conductor pads.