Multi-Layer Wiring Substrate Via-Land Shift for Signal Density
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Solution Overview
Problem
Current semiconductor devices face limitations in achieving high-density signal transmission paths due to constraints in wiring layout and density, particularly when increasing the number of electrode terminals and signal paths, which hinders efficient signal input and output from semiconductor chips.
Innovation Solution
The semiconductor device employs a multi-layer wiring substrate with strategically arranged pads, via-lands, and via-wirings, where the first and second via-lands are alternately positioned along the semiconductor chip's sides, allowing for a higher density of signal transmission paths without increasing the mounting area, and includes a design that shifts via-lands away from the chip's center to reduce stress and prevent interface fractures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of electrode terminals and signal paths is increased, then the terminal count and signal transmission capability are improved, but the wiring density and arrangement space are insufficient
Solution Approach 1:
The patent transitions from planar wiring arrangement to three-dimensional multi-layer wiring structure. Lead-out wirings are arranged across multiple wiring layers (first wiring layer, second wiring layer, third wiring layer), utilizing the vertical dimension to increase wiring capacity without expanding the substrate area. This allows numerous signal paths to be packed into a compact footprint by distributing them across different layers.
Solution Approach 2:
The patent implements nested wiring structures where wirings on different layers are positioned to overlap or align vertically. For example, lead-out wirings on the second wiring layer are arranged to overlap with land patterns, and via-lands connect wirings between layers in a nested configuration. This nesting approach maximizes space utilization and enables high-density terminal arrangement.
2Quantity of substance
If lead-out wirings are arranged on multiple wiring layers, then the wiring density is improved, but the wiring layout complexity increases
Solution Approach 1:
The patent divides the wiring structure into multiple distinct layers, each with specific functions. The first wiring layer contains pads and initial lead-out wirings, the second wiring layer contains additional lead-out wirings and land patterns, and the third wiring layer contains final lead-out wirings. This segmentation allows complex wiring functions to be distributed across simpler, more manageable layers, reducing overall layout complexity while maintaining high wiring density.
Solution Approach 2:
The patent introduces via-lands as intermediary elements that connect wirings between different layers. These via-lands serve as mediators that simplify the connection process between layers, providing standardized interfaces for inter-layer wiring connections. This intermediary structure reduces the complexity of direct multi-layer wiring connections by establishing a systematic connection protocol through the via-lands.
3Quantity of substance
If via-lands are positioned close to the semiconductor chip, then the wiring density is improved, but the risk of interface fractures increases
Solution Approach 1:
The patent applies different positioning strategies for via-lands depending on their location and function. Via-lands are positioned at optimized distances from the semiconductor chip, with some via-lands closer to the chip for space efficiency and others positioned farther away for stress relief. This localized quality adjustment allows the structure to simultaneously achieve high wiring density in critical areas while maintaining reliability in stress-prone regions.
Solution Approach 2:
The patent employs asymmetric positioning of via-lands relative to the semiconductor chip and land patterns. Rather than uniform distribution, via-lands are strategically placed at non-uniform intervals and positions, with some via-lands offset from direct alignment with land patterns. This asymmetric arrangement reduces stress concentration at symmetric points and distributes mechanical loads more evenly, thereby reducing interface fracture risk while maintaining wiring density.
Data Source
AI summary
A semiconductor device includes a wiring substrate having: a first wiring layer having pads; and a second wiring layer having wirings and via-lands. The via-lands include: first-row via-lands connected to first-row pads of the pads, respectively; and second-row via-lands connected to the second-row pads of the pads, respectively. In the perspective plan view, the first-row via-lands have: first via-lands arranged such that a center of each of the first via-lands is shifted in a direction away from a first side of the semiconductor chip than a position overlapping with a center of the corresponding first-row pad; and second via-lands arranged such that a center of each of the second via-lands arranged at a position closer to the first side than the first via-land. In the perspective plan view, the first and second via-lands are alternately arranged in a first direction along the first side.