Wiring Substrate Layout for Thermal Expansion Warpage Control
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Solution Overview
Problem
The challenge is to address the warpage issue caused by the difference in thermal expansion coefficients between the upper and lower portions of a wiring substrate, which affects the structural stability of semiconductor packages.
Innovation Solution
A wiring substrate design that includes a core portion with a bridge chip and a dummy structure, where the thermal expansion coefficient of the dummy structure is between 0.9 and 1.1 times that of the bridge chip, ensuring a matching mean thermal expansion coefficient for both the upper and lower peripheral portions, thereby reducing warpage and enhancing structural stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wiring substrate is designed with different upper and lower peripheral portions, then functional requirements are met, but warpage occurs due to thermal expansion coefficient mismatch
Solution Approach 1:
The patent applies local quality by introducing a dummy structure with specific thermal expansion properties at the lower peripheral portion. This dummy structure has a thermal expansion coefficient between 0.9 and 1.1 times that of the bridge chip, creating a localized thermal compensation zone that balances the overall thermal expansion between upper and lower portions, thereby preventing warpage while maintaining functional asymmetry.
Solution Approach 2:
The patent changes the thermal expansion parameter by selecting materials for the dummy structure with carefully controlled thermal expansion coefficients (0.9-1.1 times that of the bridge chip). This parameter adjustment ensures that the mean thermal expansion coefficients of upper and lower peripheral portions are substantially equal, resolving the warpage issue caused by thermal mismatch.
2Shape
If thermal expansion coefficients are matched between upper and lower portions, then warpage is reduced, but additional dummy structures and materials are required
Solution Approach 1:
The patent uses copying by creating a dummy structure that replicates the thermal expansion characteristics of the bridge chip. The dummy structure is positioned to overlap with the bridge chip in plan view, creating a thermal expansion mirror image that compensates for asymmetry. This copying approach simplifies the solution by using material selection rather than complex geometric arrangements.
3Adaptability or versatility
If multiple semiconductor chips are integrated in a single package, then functionality and performance are improved, but thermal expansion mismatch between chips and substrate causes warpage
Solution Approach 1:
The patent directly addresses thermal expansion by designing the dummy structure with a thermal expansion coefficient specifically tuned to match the bridge chip (within 0.9-1.1 times range). This thermal expansion matching creates balanced mean thermal expansion coefficients between upper and lower peripheral portions, preventing warpage that would otherwise result from integrating multiple semiconductor chips with different thermal properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces or prevents warpage in the wiring substrate by matching the thermal expansion coefficients, leading to improved structural stability and reliability of semiconductor packages.
Implementation Method 1
A thermal expansion coefficient of the dummy chip may be between 0.9 and 1.1 times a thermal expansion coefficient of the bridge chip
Data Source
AI summary
A wiring substrate may include a core portion, an upper peripheral portion on a top surface of the core portion, and a lower peripheral portion on a bottom surface of the core portion. The upper peripheral portion may include a bridge chip provided on the top surface of the core portion, upper insulating patterns provided on the top surface of the core portion to cover the bridge chip, and upper interconnection patterns in the upper insulating patterns. The lower peripheral portion may include a dummy structure on the bottom surface of the core portion, lower insulating patterns on the bottom surface of the core portion to cover the dummy structure, and lower interconnection patterns in the lower insulating patterns. A mean thermal expansion coefficient of the upper peripheral portion may be substantially equal to a mean thermal expansion coefficient of the lower peripheral portion.