Wiring Test Pattern Structure for Thermal-Stable Defect Detection
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Solution Overview
Problem
The challenge in semiconductor packaging is the formation of fine conductive circuit layers, which are prone to defects such as thickness or width deviations, leading to reduced yield and potential open circuits due to cracking or breaking, necessitating effective defect detection during manufacturing.
Innovation Solution
A wiring structure incorporating a test pattern layer with a heat dissipating structure adjacent to the test circuit pattern, and an etching buffer layer to prevent delamination, allows for the simulation of conductive line conditions and detection of defects by measuring sheet resistance, thereby ensuring accurate thickness and width assessment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If power is applied to the test circuit pattern for defect detection, then electrical performance measurement is improved, but temperature rise occurs which may cause false defects or open circuits
Solution Approach 1:
The heat dissipating structure serves as an intermediary thermal management component positioned adjacent to the test circuit pattern. It acts as a heat sink that absorbs and dissipates heat generated during electrical testing, preventing temperature rise that could cause false defects or open circuits while allowing accurate electrical performance measurement
Solution Approach 2:
The heat dissipating structure is pre-positioned adjacent to the test circuit pattern before electrical testing begins. This proactive thermal management structure is already in place to cushion against temperature rise during power application, preventing thermal-related testing failures before they occur
2Manufacturing precision
If the test circuit pattern is made finer to match production circuit requirements, then manufacturing relevance is improved, but susceptibility to defects such as cracking and breaking increases
Solution Approach 1:
The test circuit pattern is designed as a simplified copy of the production circuit pattern, replicating the same conductive layer structure, materials, and geometric dimensions. This allows the test pattern to accurately represent production circuit behavior including susceptibility to defects, while being accessible for dedicated testing without affecting functional circuits
Solution Approach 2:
The substrate structure is segmented into distinct functional regions: production circuit regions for manufacturing and test pattern regions for detection. The test pattern layer is separated from the circuit pattern layer, allowing independent testing of fine conductive structures without risking damage to functional production circuits
3Device complexity
If the test pattern layer is integrated with the circuit pattern layer, then structural compactness is improved, but delamination between layers may occur affecting test accuracy
Solution Approach 1:
The etching buffer layer serves as an intermediary protective layer positioned between the test circuit pattern and the dielectric layer. It prevents direct contact between the conductive pattern and dielectric during etching processes, eliminating a primary cause of delamination while maintaining clear layer integration for structural compactness
Solution Approach 2:
The etching buffer layer is applied beforehand during the manufacturing process to protect the interface between the test circuit pattern and dielectric layer. This proactive protective measure prevents delamination from occurring during subsequent etching steps, ensuring layer stability throughout production
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces temperature rise during electrical current application, prevents delamination, and allows for precise detection of defects in the conductive circuit layers, enhancing manufacturing yield and preventing open circuits.
Implementation Method 1
The heat dissipating structure is disposed adjacent to the test circuit pattern, and is configured to reduce temperature rise of the test circuit pattern when a power is applied to the test circuit pattern
Implementation Method 2
The etching buffer layer is disposed adjacent to the test circuit pattern, and is configured to reduce a delamination between the test circuit pattern and the dielectric layer
Data Source
AI summary
A wiring structure includes a test pattern layer. The test pattern layer includes a test circuit pattern and a heat dissipating structure. The heat dissipating structure is disposed adjacent to the test circuit pattern, and is configured to reduce temperature rise of the test circuit pattern when a power is applied to the test circuit pattern.