Wafer Level Chip Scale Package Conductive Pattern Design
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Solution Overview
Problem
Conventional wafer level chip scale packages have limited contact surface area between solder balls and ball pad sections, leading to reliability issues and increased parasitic capacitance due to the circular shape of ball pad sections.
Innovation Solution
The design includes conductive patterns on ball pad sections that protrude from the first dielectric layer, exposing a portion of it, which increases the contact area with solder balls and reduces parasitic capacitance by using a spiral or mesh shape, enhancing joint reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If circular ball pad sections are used, then the structure is simple and easy to manufacture, but the contact surface area between solder balls and ball pads is limited and parasitic capacitance increases
Solution Approach 1:
The ball pad section is divided into multiple conductive patterns (first, second, and third conductive patterns) arranged in specific configurations. This segmentation increases the total contact surface area between the solder ball and the ball pad section while distributing the electrical connection across multiple pathways, thereby improving joint reliability without creating a single point of failure.
Solution Approach 2:
The conductive patterns are arranged in three-dimensional spatial configurations including vertical stacking and angular orientations (e.g., 45-degree angles). This dimensional arrangement maximizes the contact surface area within the limited ball pad footprint while reducing parasitic capacitance by optimizing the electrical field distribution across multiple layers and directions.
2Reliability
If larger contact surface area is achieved, then joint reliability improves, but parasitic capacitance may increase
Solution Approach 1:
Different conductive patterns are positioned at specific locations within the ball pad section to optimize local electrical properties. The first conductive pattern provides primary contact, while the second and third patterns are strategically placed to enhance reliability without creating excessive capacitance. This local optimization ensures that each region contributes appropriately to both mechanical strength and electrical performance.
Solution Approach 2:
The conductive patterns employ asymmetric geometries and arrangements, such as elongated shapes in specific directions and non-uniform spacing between patterns. This asymmetry reduces parasitic capacitance by minimizing the effective electrical field area while maintaining sufficient mechanical contact area, thereby decoupling the two competing requirements for improved joint reliability.
Data Source
AI summary
Provided is a wafer level chip scale package that reduces the parasitic capacitance generated between ball pads and the solder balls, and enhances the joint reliability between the ball pads and the solder balls. The wafer level chip scale package provides a conductive pattern in each ball pad section, on which a solder ball is mounted, so as to have a spiral or mesh shape, provides a space defined by the conductive pattern such that a first dielectric layer under the conductive pattern is exposed, and provides the solder ball on a top surface of each ball pad section such that part of the solder ball is inserted into the space defined by the conductive pattern. When viewed from the top, the dielectric layer is exposed from each ball pad section by an area of about 50% or less.