Wafer Level Chip Scale Package Stress Relief Grooves
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Solution Overview
Problem
Conventional semiconductor devices with resin-based insulating and sealing layers face issues of substrate curvature and terminal short-circuits due to elastic deformation and stress, which existing groove-based solutions inadequately address.
Innovation Solution
A semiconductor device design featuring a semiconductor substrate with a first insulating section, a conductive section, a second insulating section with openings to expose the conductive section, and a third insulating section with a third opening that passes through both, allowing stress absorption and preventing curvature and short-circuits by exposing the first insulating section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If resin-based insulating layer and sealing layer are formed to cover the substrate, then insulation and sealing are improved, but stress is generated causing substrate curvature and layer separation
Solution Approach 1:
The insulating layer and sealing layer are divided into multiple sections by grooves formed between adjacent terminals. This segmentation allows each section to independently accommodate stress from resin contraction and thermal expansion, preventing cumulative stress from causing substrate curvature or layer separation while maintaining insulation and sealing functions.
2Shape
If narrow grooves are formed to divide insulating and sealing layers, then substrate curvature is reduced, but elastic deformation cannot be completely absorbed and terminal short-circuit risk remains
Solution Approach 1:
The grooves are positioned specifically between adjacent terminals where stress concentration occurs. By concentrating the stress-relief function at these critical locations rather than uniformly across the substrate, the design effectively absorbs elastic deformation from resin contraction and thermal expansion while maintaining insulation between terminals through the localized stress management.
3Productivity
If terminals are highly integrated to increase density, then area efficiency is improved, but insulation between terminals deteriorates and short-circuit risk increases
Solution Approach 1:
Grooves are formed between adjacent terminals to divide the insulating and sealing layers into separate sections. This segmentation creates physical barriers that prevent stress-induced deformation from compromising terminal insulation, allowing terminals to be placed closer together for high integration density while maintaining reliable electrical isolation.
4Stability of the object's composition
If grooves are formed to reduce stress, then layer separation is prevented, but manufacturing complexity increases
Solution Approach 1:
The groove formation process is combined with existing fabrication steps such as photolithography and etching that are already used for terminal patterning. By integrating groove formation into the existing manufacturing flow rather than adding a separate process, the design improves layer adhesion and prevents separation while minimizing increases in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The third opening effectively absorbs stress and prevents curvature of the substrate and separation of insulating layers, while reducing the risk of electrical malfunctions such as short circuits between highly integrated terminals.
Implementation Method 1
the insulating layer and the sealing layer are usually formed of resin. Since resin layers can contract during curing, or undergo elastic deformation when heated, stress is generated between the insulating layer and the sealing layer, and the substrate.
Implementation Method 2
Since resin layers can contract during curing, or undergo elastic deformation when heated, stress is generated between the insulating layer and the sealing layer, and the substrate.
Data Source
AI summary
A semiconductor device of the invention includes a semiconductor substrate having a first insulating section formed on one surface thereof. A first conductive section is disposed on the one surface of the semiconductor substrate. A second insulating section is superimposed over the first insulating section and covers the first conductive section. A second conductive section is superimposed over the second insulating section. A third insulating section is disposed over the second insulating section and covers the second conductive section. These first conductive section, second insulating section, second conductive section, third insulating section, and terminal altogether constitute a structure. A third opening is formed between adjacent structures. The third opening is formed passing through the third and second insulating sections to expose the first insulating section.