Wide-Band WLAN Transceiver LO Architecture for 2.4/5/6 GHz Support
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Solution Overview
Problem
Current WLAN transceivers lack the capability to efficiently support multiple frequency bands, particularly the 2.4 GHz, 5 GHz, and 6 GHz bands, limiting their operational flexibility and coverage.
Innovation Solution
A transceiver design that includes a diplexer, frontend circuits, transmitter and receiver baseband circuits, a digital signal processor, and a frequency synthesizer, which uses local oscillators and clock multipliers to enable up-conversion and down-conversion across the 2.4 GHz, 5 GHz, and 6 GHz frequency ranges, allowing for seamless operation across all three bands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a transceiver is designed to support multiple frequency bands (2.4 GHz, 5 GHz, and 6 GHz), then the operational flexibility and coverage are improved, but the device complexity increases
Solution Approach 1:
The transceiver is designed with universal components that can handle multiple frequency bands. The diplexer enables a single antenna to serve multiple bands (2.4 GHz, 5 GHz, and 6 GHz), while the frequency synthesizer generates multiple LO signals for different bands using a unified architecture. This multi-functional design allows one transceiver to replace what would traditionally require multiple separate transceivers, improving versatility without proportionally increasing complexity.
Solution Approach 2:
The transceiver architecture is segmented into independent functional blocks: a diplexer for frequency separation, frontend circuits for signal processing, and a frequency synthesizer for LO generation. Each segment handles specific frequency ranges or functions, allowing the system to support multiple bands through modular operation. This segmentation enables flexible band selection and simplifies the overall design by dividing the complex multi-band operation into manageable, independent segments.
2Reliability
If separate transceivers are used for each frequency band, then the performance for each band is optimized, but the overall device complexity and resource usage increase
Solution Approach 1:
The patent merges the functionality of multiple band-specific transceivers into a single unified transceiver. The diplexer combines signal paths for 2.4 GHz, 5 GHz, and 6 GHz bands into one antenna interface, while the frequency synthesizer consolidates LO generation for all bands into one circuit. This merging maintains band-specific performance optimization through dedicated frontend circuits for each band while eliminating the need for separate transceiver hardware, thereby reducing overall device complexity and resource usage.
3Device complexity
If a unified transceiver architecture is used for all bands, then the device complexity is reduced, but the measurement precision and signal quality may deteriorate
Solution Approach 1:
While maintaining a unified transceiver architecture, the patent segments the signal processing path into band-specific frontend circuits. Each frontend circuit (first frontend for 5/6 GHz, second frontend for 2.4 GHz) is dedicated to specific frequency ranges, ensuring optimized signal conversion accuracy for each band. This segmentation within the unified architecture allows the system to maintain high measurement precision and signal quality for each band while benefiting from the complexity reduction of a shared overall structure.
Solution Approach 2:
The unified transceiver implements local quality optimization by providing dedicated frontend circuits with optimized components and parameters for each specific frequency band. The first frontend circuit is optimized for 5 GHz and 6 GHz operations, while the second frontend circuit is optimized for 2.4 GHz operations. This local optimization ensures that each band receives the appropriate signal processing quality while the overall unified architecture maintains reduced complexity through shared components like the diplexer and frequency synthesizer.
Data Source
AI summary
A method includes generating a reference clock using a crystal oscillator; generating a first clock based on the reference clock using a clock multiplier unit, in which a frequency of the first clock is higher than a frequency of the reference clock by a clock multiplier factor; generating a second lock based on the first clock using a frequency multiplying circuit in accordance with a frequency multiplying signal, in which a frequency of the second clock is higher than the frequency of the first clock by a factor that is equal to either five fourths or three halves, depending on whether the frequency multiplying signal is in a first state or in a second state; dividing down the second clock by a factor of two to generate a first LO (local oscillator) signal; dividing down the first LO signal by a factor of two to generate a second LO signal.