Wafer Level Chip Scale Package with Conductive Cover Plate Insulation

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Solution Overview

Problem

Wafer level chip scale packaging technologies face challenges in achieving low packaging costs, mechanical strength, and effective heat dissipation while maintaining compact dimensions, which restricts flexible wiring and adhesion to printed circuit boards.

Innovation Solution

A packaging method involving a conductive cover plate with adhesive layers and insulation material to form a first insulation structure around the chip, along with a second insulation structure for electrode windows, reduces complexity and costs, enhances mechanical support, and improves heat dissipation by completely covering the chip circumference with insulation material.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If wafer level chip scale packaging is used to achieve compact dimensions, then packaging cost and product size are reduced, but mechanical strength and heat dissipation capability are insufficient

Engineering Contradiction:

Improvepackaged chip sizeVSAvoidmechanical strength

Core Design Contradiction:

Volume of moving objectVSStrength

Solution Approach 1:

The patent uses a composite packaging structure combining conductive cover plate (metal), insulation material (resin or ceramic), and adhesive layers. This composite approach provides both compact dimensions and enhanced mechanical strength, resolving the contradiction between small size and structural strength.

Inventive Principle:

Principle #40Composite materials

2Volume of moving object

If wafer level chip scale packaging is used to reduce packaging size, then heat dissipation area is limited, but effective heat dissipation is needed for high-performance devices

Engineering Contradiction:

Improvepackaged chip sizeVSAvoidheat dissipation capability

Core Design Contradiction:

Volume of moving objectVSTemperature

Solution Approach 1:

The conductive cover plate acts as a thermal intermediary, directly contacting the chip's heat-generating surfaces and conducting heat away efficiently. The insulation material surrounding the chip provides additional thermal management pathways, enabling effective heat dissipation within the compact package.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Strength

If traditional individual chip packaging is used, then mechanical strength and heat dissipation are improved, but packaging cost and production complexity increase

Engineering Contradiction:

Improvemechanical strengthVSAvoidpackaging process complexity

Core Design Contradiction:

StrengthVSDevice complexity

Solution Approach 1:

The patent merges multiple chips onto a single carrier with a common conductive cover plate and shared insulation structures. This consolidation reduces the number of separate packaging operations, lowers production complexity, and maintains mechanical strength through the unified protective structure.

Inventive Principle:

Principle #5Merging (Combining)

4Reliability

If insulation material completely covers chip circumference, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvepackaged chip reliabilityVSAvoidmanufacturing ease

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent uses vacuum suction through holes in the conductive cover plate to automatically fill insulation material around the chip circumference. This pneumatic/hydraulic approach ensures complete coverage for reliability while automating the process to maintain manufacturing ease.

Inventive Principle:

Principle #29Pneumatics and hydraulics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method significantly reduces packaging costs and complexity, enhances mechanical strength and heat dissipation, and improves the reliability of the packaged chip, making it suitable for high-performance, compact electronic devices.

Implementation Method 1

forming a plurality of adhesive layers on a surface of the corresponding chips; covering a conductive cover plate, bonding the conductive cover plate with the chips through the adhesive layers

Methodology Applied

Scientific EffectAdhesion: Adhesive

Implementation Method 2

providing an insulation material to fill the packaging spaces through via holes on the conductive cover plate

Methodology Applied

Scientific EffectCapillary action: Capillary Action

Data Source

PatentUS9299592B2Package structure and packaging method of wafer level chip scale package

Publication Date: 2016.03.29 NIKO SEMICON

AI summary

A package structure and a packaging method of wafer level chip scale package are provided. The packaging method includes: providing a carrier, and disposing a plurality of chips on the carrier; forming a plurality of adhesive layers on a surface of the corresponding chips; covering a conductive cover plate, bonding the conductive cover plate with the chips through the adhesive layers, and dividing out a plurality of packaging spaces by the conductive cover plate for disposing the chips respectively; and providing an insulation material to fill the packaging spaces through via holes on the conductive cover plate to form a first insulation structure; finally, removing the carrier.