Wafer Level Chip Scale Package Eliminating Encapsulation Warpage
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Solution Overview
Problem
Conventional wafer level chip scale packages face issues with contamination from typical encapsulation materials and require costly hard cure processes, which can lead to warpage due to mismatched thermal expansion coefficients of packaging materials.
Innovation Solution
A wafer level chip scale package design that eliminates traditional encapsulation, using a first and second dielectric layer with matching thermal expansion coefficients, and a redistribution layer with under bump metals and solder balls, fabricated through a process involving precise photoetching and printing, without the need for hard cure processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If typical encapsulation materials are used, then the semiconductor dies are protected, but contamination occurs and warpage develops due to mismatched thermal expansion coefficients
Solution Approach 1:
The patent removes the traditional encapsulation material (mold compound) from the packaging structure and replaces it with dielectric layers that are deposited directly on the semiconductor die. This extraction of the harmful encapsulation material eliminates the source of contamination and thermal expansion mismatch, while maintaining the protective function through alternative structural means.
Solution Approach 2:
The patent changes the material parameters by using dielectric layers with thermal expansion coefficients that match the semiconductor die, rather than using typical encapsulation materials with mismatched coefficients. This parameter matching prevents warpage during temperature cycling while maintaining structural integrity and protection.
2Ease of manufacture
If hard cure processes are used, then the encapsulation material is cured, but fabrication costs increase and warpage occurs due to thermal expansion mismatch
Solution Approach 1:
The patent eliminates the hard cure process by removing the encapsulation material that requires such processing. Instead, dielectric layers are deposited and patterned using standard semiconductor fabrication processes that do not involve high-temperature hard curing, thereby avoiding both the cost increase and warpage issues associated with hard cure processes.
3Reliability
If traditional encapsulation is used, then the semiconductor dies are encapsulated, but contamination risks increase and fabrication costs increase
Solution Approach 1:
The patent changes the material composition from traditional encapsulation materials to dielectric layers that are compatible with semiconductor fabrication processes. This material substitution eliminates contamination risks associated with encapsulation materials while reducing fabrication costs by using standard deposition and patterning processes instead of specialized encapsulation processes.
Data Source
AI summary
A wafer level chip scale package includes a first dielectric layer having a first surface, a second surface, and a main through hole passing through the first dielectric layer between the first and second surfaces. A semiconductor die is disposed in the main through hole of the first dielectric layer and including a bond pad disposed away from the first surface of the first dielectric layer. A redistribution layer is electrically connected to the bond pad of the semiconductor die and extends along the second surface of the first dielectric layer. A second dielectric layer covers the first dielectric layer and the redistribution layer and has an opening exposing the redistribution layer. An under bump metal fills the opening of the second dielectric layer and is electrically connected to the redistribution layer. A solder ball is electrically connected to the under bump metal.