Wafer Level Chip Scale Package Thick Bottom Metal Support

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Solution Overview

Problem

Conventional wafer level chip scale packages (WLCSP) lack mechanical support and optimized thermal performance, and the exposure of the back surface metal contact results in poor moisture resistance and mechanical protection.

Innovation Solution

A method for creating a molded wafer level chip scale package with a thick bottom metal, involving the formation of through vias, insulation layers, and a conductive material connection to the back surface, along with a lead frame and package material to provide mechanical support and improved heat dissipation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If the chip is thinned to reduce substrate resistance and package thickness, then the package size and resistance are improved, but the chip becomes more prone to breaking and damage

Engineering Contradiction:
Improvechip thicknessVSAvoidchip mechanical strength
Core Design Contradiction:
Length of stationary objectVSStrength

Solution Approach 1:

The patent applies beforehand cushioning by forming a thick bottom metal layer and providing mechanical support structures before the chip thinning process. This pre-established support system prevents chip breakage during and after thinning, allowing the chip to be thinned to the required thickness without compromising mechanical integrity.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The patent uses composite materials by combining the thinned chip with a thick bottom metal layer and package material to create a hybrid structure. The composite construction provides both the thin profile needed for low resistance and the mechanical strength required to prevent breakage, resolving the contradiction between thickness reduction and strength maintenance.

Inventive Principle:
Principle #40Composite materials

2Ease of manufacture

If the back surface metal contact is exposed to achieve simple structure, then manufacturing is easier, but moisture resistance and mechanical protection deteriorate

Engineering Contradiction:
Improvepackaging simplicityVSAvoidmoisture resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces an intermediary package material that covers and protects the exposed back surface metal contact. This intermediary layer acts as a barrier against moisture and mechanical damage while maintaining the simplicity of the manufacturing process, thus resolving the contradiction between ease of manufacture and moisture resistance.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If conventional packaging methods are used to simplify the package structure, then device complexity is reduced, but thermal performance and mechanical support are insufficient

Engineering Contradiction:
Improvepackage structure complexityVSAvoidthermal performance
Core Design Contradiction:
Device complexityVSTemperature

Solution Approach 1:

The patent replaces the conventional mechanical packaging structure with a optimized thermal structure featuring a thick bottom metal layer that serves as a heat sink. This substitution improves thermal performance by providing a low-resistance thermal path while maintaining relatively simple device complexity, as the same metal layer serves both structural and thermal functions.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS9224679B2Wafer level chip scale package with exposed thick bottom metal
Publication Date: 2015.12.29 ALPHA & OMEGA SEMICONDUCTOR INC
  • US9224679B2 patent drawing
  • US9224679B2 patent drawing
  • US9224679B2 patent drawing

AI summary

A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.