Wafer Level Chip Scale Package Back Electrode Connection via Trench Etching
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Solution Overview
Problem
In wafer level chip scale packaging, existing methods face challenges in connecting the back electrode layer of semiconductor devices without extending conductive structures to cutting portions, which can increase tool attrition during the cutting process and affect package structure separation.
Innovation Solution
A manufacturing method is developed where a trench is formed in the channel portion to connect the back electrode layer with a conductive structure, and the cutting process is performed along the cutting portion without extending the conductive structure, reducing tool attrition and enabling efficient separation of package structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conductive structure is extended to the cutting portion to connect the back electrode layer, then the electrical connection is improved, but the cutting tool attrition increases and package structure separation becomes difficult
Solution Approach 1:
The outer region is divided into a cutting portion and a channel portion, with the conductive structure confined to the channel portion only. This segmentation allows the cutting tool to avoid the conductive structure during separation, reducing tool attrition while maintaining electrical connection functionality in the non-cutting area.
Solution Approach 2:
The conductive structure is selectively placed only in the channel portion where electrical connection is needed, while the cutting portion remains free of conductive structures. This localized quality ensures that the back electrode layer is electrically connected where required, but the cutting area remains suitable for clean separation without tool damage.
2Reliability
If the conductive structure is extended to the cutting portion to connect the back electrode layer, then the electrical connection is improved, but the package structure separation becomes difficult
Solution Approach 1:
The outer region is segmented into cutting and channel portions, with the conductive structure confined to the channel portion. This segmentation enables clean separation at the cutting portion without disrupting the electrical connection in the channel portion, facilitating easier package structure separation.
Solution Approach 2:
The conductive structure is extracted from the cutting portion and retained only in the channel portion. This extraction eliminates the conflict between electrical connection requirements and separation requirements, allowing the cutting portion to be cleanly separated without the conductive structure interfering with the process.
3Object-generated harmful factors
If the conductive structure is confined to the channel portion only, then the cutting tool attrition is reduced, but the electrical connection path may be insufficient
Solution Approach 1:
The conductive structure extends vertically through the trench in the channel portion to connect the back electrode layer to the active surface, creating a three-dimensional connection path. This dimensional approach ensures sufficient electrical connection capability within the confined channel portion without requiring horizontal extension into the cutting portion.
Solution Approach 2:
The trench filled with conductive material serves as an intermediary structure that provides the electrical connection path from the back electrode layer to the active surface within the channel portion. This intermediary structure achieves the electrical connection function without requiring the conductive structure to extend to the cutting portion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for effective electrical connection of the back electrode layer while minimizing cutting tool attrition and facilitating the separation of package structures, enhancing the manufacturing efficiency and reliability of wafer level chip scale packages.
Implementation Method 1
an etching process is performed to form a trench exposing the back electrode layer at the channel portion
Implementation Method 2
the cutting tool of the cutting machine is used to cut the semiconductor material and a thinner back electrode layer instead of a thicker metal material layer
Data Source
AI summary
A manufacturing method of wafer level chip scale package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided. An active surface of one of the semiconductor devices has an active an active region and an outer region. A first electrode and a second electrode are arranged on the active region, and the outer region has a cutting portion and a channel portion. Next, a patterned protecting layer having a plurality of openings is formed on the active surface to respectively expose the first and second electrodes and channel portion. Subsequently, a wafer back thinning process is performed and then a back electrode layer is deposited. Subsequently, the channel portion is etched to form a trench exposing the back electrode layer, and a conductive structure connected to the back electrode layer is formed through the trench. Thereafter, the wafer is cut along the cutting portion.