Wafer-Level Chip Scale Package Sidewall Encapsulation
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Solution Overview
Problem
Current wafer level chip scale packages (WLCSP) are susceptible to damage such as cracking and chipping during the wafer saw or package singulation process, which can lead to functional failures, necessitating a need for reliable and cost-effective protection methods.
Innovation Solution
A method involving the formation of a semiconductor package with an encapsulant material that covers at least a portion of the sidewalls of the die, providing a protective layer to prevent damage during singulation and assembly processes, using materials like mold compounds, epoxy, or silicone-based materials applied through techniques such as film-assisted molding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If WLCSP is used to reduce package size, then packaging efficiency is improved, but susceptibility to damage during singulation increases
Solution Approach 1:
The patent applies preliminary action by forming the encapsulant material to cover the sidewalls of the die before the singulation process. This protective layer is prepared in advance to prevent damage during the subsequent wafer saw or singulation operations, allowing WLCSP to maintain both small size and high reliability.
2Reliability
If encapsulant material is applied to protect sidewalls, then damage resistance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs flexible shells and thin films by using an encapsulant material that forms a thin protective layer over the sidewalls of the die. This approach provides effective damage resistance while maintaining relatively simple manufacturing processes, as the encapsulant can be applied as a conformal coating or thin film structure.
Data Source
AI summary
Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a wafer having first and second major surfaces. The wafer is prepared with a plurality of dies and a plurality of external electrical contacts disposed on the first major surface of the wafer. The method includes processing the wafer. Processing the wafer includes separating the wafer into a plurality of individual dies. An individual die includes first and second major surfaces and first and second sidewalls, and the external electrical contacts are formed on the first major surface of the die. An encapsulant material is formed. The encapsulant material covers at least a portion of the first and second sidewalls of the die.