WLCSP Bump Stack Structure for Thermal Stress Relief
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Solution Overview
Problem
Semiconductor devices, particularly Wafer Level Chip Scale Packages (WLCSP) with large semiconductor dies, face stress-related issues such as bump cracking and delamination due to thermal and mechanical stress during temperature cycling, leading to interconnect defects and decreased production yield.
Innovation Solution
A method involving the formation of a dampening structure under the bumps in WLCSPs, which includes creating grooves in insulating layers to increase the thickness and contact area of conductive layers, thereby reducing stress and improving bonding strength, and using a compliant island or polymer support layer to redistribute thermal and mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnect structures are used in WLCSP with large semiconductor dies, then manufacturing is simpler, but stress-related defects such as bump cracking and delamination occur during temperature cycling
Solution Approach 1:
The interconnect structure is segmented into multiple conductive layers (first conductive layer, second conductive layer, third conductive layer) stacked vertically, with each layer providing specific structural support and stress distribution functions. This segmentation allows the structure to better handle thermal and mechanical stresses while maintaining manufacturing feasibility through standardized layer-by-layer fabrication processes.
Solution Approach 2:
The interconnect structure uses composite construction with multiple materials including conductive layers (copper, aluminum, or alloy), insulating layers (dielectric materials), and bonding layers, creating a multi-material stack that optimizes both mechanical strength and electrical conductivity while reducing stress concentration points.
2Strength
If thicker conductive layers are used to reduce stress, then bonding strength improves, but manufacturing complexity and cost increase
Solution Approach 1:
Instead of increasing conductive layer thickness in a single dimension, the solution distributes conductive material across multiple vertical layers, transitioning from a planar thick-layer approach to a stacked multi-layer architecture. This dimensional transition maintains bonding strength while enabling thinner individual layers that are easier to manufacture with standard deposition processes.
Solution Approach 2:
Different conductive layers are positioned at specific locations within the interconnect structure to provide localized stress distribution. The first conductive layer is adjacent to the semiconductor die, the second layer is positioned intermediate, and the third layer is at the bump interface, with each layer tailored to address stress conditions at its specific location.
Data Source
AI summary
A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.