Wafer-Level Chip-Scale Package Bump Assemblies Mitigating Stress Failures
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Solution Overview
Problem
Wafer-level packaging technologies face limitations in handling stress caused by coefficient of thermal expansion (CTE) mismatch and dynamic deformation during thermal cycling and drop tests, particularly for larger integrated circuit chips, leading to solder bump failures.
Innovation Solution
The implementation of wafer-level chip-scale package devices with two arrays of bump assemblies, where one array is configured to withstand higher stress levels than the other, using larger solder bumps with different compositions and interface configurations to distribute stress and maintain coplanarity, reducing the likelihood of failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If wafer-level packaging is used for larger integrated circuit chips, then chip size and integration capability are improved, but stress-related failures increase due to CTE mismatch and dynamic deformation
Solution Approach 1:
The patent applies different bump configurations to different regions of the chip. Specifically, corner bumps have larger diameters than edge bumps, which in turn are larger than center bumps. This local differentiation allows each region to withstand the specific stress patterns it experiences during thermal cycling and drop tests, resolving the contradiction between using larger chips and maintaining reliability.
Solution Approach 2:
The patent changes the physical parameters of the solder bumps based on their location. The bump diameter varies from corner to center, and the bump heights are adjusted to maintain coplanarity while accommodating different stress conditions. These parameter changes enable larger chips to be packaged reliably by adapting the bump characteristics to local stress requirements.
2Ease of manufacture
If uniform bump configurations are used across the chip, then manufacturing simplicity is maintained, but stress distribution is uneven leading to higher failure rates
Solution Approach 1:
Instead of uniform bumps, the patent implements a graduated bump structure where corner bumps are largest, edge bumps are medium-sized, and center bumps are smallest. This local quality approach ensures that bumps in high-stress corner regions can withstand greater forces, while center bumps suffice for lower-stress areas, thereby improving reliability without significantly complicating manufacturing.
3Reliability
If larger solder bumps are used to withstand higher stress, then reliability under stress is improved, but coplanarity and stress distribution across the chip deteriorate
Solution Approach 1:
The patent differentiates bump sizes by location, with larger bumps at corners and smaller bumps at the center.配合underbump metallization structures, this local quality approach allows each bump to be optimally sized for its position while maintaining overall coplanarity through controlled metallization layers, thus achieving both stress withstand capability and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of wafer-level chip-scale package devices by reducing stress-related failures and electromigration susceptibility, allowing for the use of larger integrated circuit chips in various applications such as SOC, DRAM, and CPU.
Implementation Method 1
bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the other arrays
Implementation Method 2
stress caused by CTE mismatch during thermal cycling tests
Data Source
AI summary
Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays.